#ifndef __LPDDR5_SGR_H__
#define __LPDDR5_SGR_H__

#include "main.h"

typedef struct __LPDDR5_SGR {
	volatile uint32_t PA_QOS_URGENT_CTL;	    // 0x00
	volatile uint32_t PHY_CTL_IO_REG0;	        // 0x04
	volatile uint32_t PHY_CTL_IO_SLICE0;	    // 0x08
	volatile uint32_t PHY_CTL_IO_SLICE1;	    // 0x0c
	volatile uint32_t PHY_CTL_IO_STATUS0;	    // 0x10
	volatile uint32_t PHY_CTL_IO_STATUS1;	    // 0x14
	volatile uint32_t RSVD_0;	 				// 0x18 Reserved 0.
	volatile uint32_t RSVD_1;	 				// 0x1C Reserved 1.
	volatile uint32_t PARMASK;	                // 0x20
	volatile uint32_t PAWMASK;	                // 0x24
	volatile uint32_t RST_CTL;	                // 0x28
	volatile uint32_t DDRCTL_STATUS;	        // 0x2c
	volatile uint32_t RSVD_2;	 				// 0x30 Reserved 2.
	volatile uint32_t RSVD_3;	 				// 0x34 Reserved 3.
	volatile uint32_t RSVD_4;	 				// 0x38 Reserved 4.
	volatile uint32_t RSVD_5;	 				// 0x3C Reserved 5.
	volatile uint32_t DDRPHY_STATUS0;	        // 0x40
	volatile uint32_t DDRPHY_STATUS1;	        // 0x44
	volatile uint32_t RSVD_6;	 				// 0x48 Reserved 6.
	volatile uint32_t DDRPHY_PINS_CTL;	        // 0x4c
	volatile uint32_t DDRPHY_PINS_TEST_CTL;	    // 0x50
	volatile uint32_t DDRPHY_PINS_TEST_CTL2;	// 0x54
	volatile uint32_t DDRPHY_PINS_TEST_CTL3;	// 0x58
	volatile uint32_t DDRPHY_PINS_TEST_CTL4;	// 0x5c
	volatile uint32_t DDRPHY_PINS_TEST_CTL5;	// 0x60
	volatile uint32_t RSVD_7;	 // 0x64 Reserved 7.
	volatile uint32_t RSVD_8;	 // 0x68 Reserved 8.
	volatile uint32_t RSVD_9;	 // 0x6c Reserved 9.
	volatile uint32_t RSVD_10;	 // 0x70 Reserved 10.
	volatile uint32_t RSVD_11;	 // 0x74 Reserved 11.
	volatile uint32_t RSVD_12;	 // 0x78 Reserved 12.
	volatile uint32_t RSVD_13;	 // 0x7c Reserved 13.
	volatile uint32_t RSVD_14;	 // 0x80 Reserved 14.
	volatile uint32_t RSVD_15;	 // 0x84 Reserved 15.
	volatile uint32_t RSVD_16;	 // 0x88 Reserved 16.
	volatile uint32_t RSVD_17;	 // 0x8c Reserved 17.
	volatile uint32_t RSVD_18;	 // 0x90 Reserved 18.
	volatile uint32_t RSVD_19;	 // 0x94 Reserved 19.
	volatile uint32_t RSVD_20;	 // 0x98 Reserved 20.
	volatile uint32_t RSVD_21;	 // 0x9c Reserved 21.
	volatile uint32_t RSVD_22;	 // 0xa0 Reserved 22.
	volatile uint32_t RSVD_23;	 // 0xa4 Reserved 23.
	volatile uint32_t RSVD_24;	 // 0xa8 Reserved 24.
	volatile uint32_t RSVD_25;	 // 0xac Reserved 25.
	volatile uint32_t RSVD_26;	 // 0xb0 Reserved 26.
	volatile uint32_t RSVD_27;	 // 0xb4 Reserved 27.
	volatile uint32_t RSVD_28;	 // 0xb8 Reserved 28.
	volatile uint32_t RSVD_29;	 // 0xbc Reserved 29.
	volatile uint32_t RSVD_30;	 // 0xc0 Reserved 30.
	volatile uint32_t RSVD_31;	 // 0xc4 Reserved 31.
	volatile uint32_t RSVD_32;	 // 0xc8 Reserved 32.
	volatile uint32_t RSVD_33;	 // 0xcc Reserved 33.
	volatile uint32_t RSVD_34;	 // 0xd0 Reserved 34.
	volatile uint32_t RSVD_35;	 // 0xd4 Reserved 35.
	volatile uint32_t RSVD_36;	 // 0xd8 Reserved 36.
	volatile uint32_t RSVD_37;	 // 0xdc Reserved 37.
	volatile uint32_t RSVD_38;	 // 0xe0 Reserved 38.
	volatile uint32_t RSVD_39;	 // 0xe4 Reserved 39.
	volatile uint32_t RSVD_40;	 // 0xe8 Reserved 40.
	volatile uint32_t RSVD_41;	 // 0xec Reserved 41.
	volatile uint32_t RSVD_42;	 // 0xf0 Reserved 42.
	volatile uint32_t RSVD_43;	 // 0xf4 Reserved 43.
	volatile uint32_t RSVD_44;	 // 0xf8 Reserved 44.
	volatile uint32_t RSVD_45;	 // 0xfc Reserved 45.
	volatile uint32_t RSVD_46;	 // 0x100 Reserved 46.
	volatile uint32_t RSVD_47;	 // 0x104 Reserved 47.
	volatile uint32_t RSVD_48;	 // 0x108 Reserved 48.
	volatile uint32_t RSVD_49;	 // 0x10c Reserved 49.
	volatile uint32_t RSVD_50;	 // 0x110 Reserved 50.
	volatile uint32_t RSVD_51;	 // 0x114 Reserved 51.
	volatile uint32_t RSVD_52;	 // 0x118 Reserved 52.
	volatile uint32_t RSVD_53;	 // 0x11c Reserved 53.
	volatile uint32_t RSVD_54;	 // 0x120 Reserved 54.
	volatile uint32_t RSVD_55;	 // 0x124 Reserved 55.
	volatile uint32_t RSVD_56;	 // 0x128 Reserved 56.
	volatile uint32_t RSVD_57;	 // 0x12c Reserved 57.
	volatile uint32_t RSVD_58;	 // 0x130 Reserved 58.
	volatile uint32_t RSVD_59;	 // 0x134 Reserved 59.
	volatile uint32_t RSVD_60;	 // 0x138 Reserved 60.
	volatile uint32_t RSVD_61;	 // 0x13c Reserved 61.
	volatile uint32_t RSVD_62;	 // 0x140 Reserved 62.
	volatile uint32_t RSVD_63;	 // 0x144 Reserved 63.
	volatile uint32_t RSVD_64;	 // 0x148 Reserved 64.
	volatile uint32_t RSVD_65;	 // 0x14c Reserved 65.
	volatile uint32_t RSVD_66;	 // 0x150 Reserved 66.
	volatile uint32_t RSVD_67;	 // 0x154 Reserved 67.
	volatile uint32_t RSVD_68;	 // 0x158 Reserved 68.
	volatile uint32_t RSVD_69;	 // 0x15c Reserved 69.
	volatile uint32_t RSVD_70;	 // 0x160 Reserved 70.
	volatile uint32_t RSVD_71;	 // 0x164 Reserved 71.
	volatile uint32_t RSVD_72;	 // 0x168 Reserved 72.
	volatile uint32_t RSVD_73;	 // 0x16c Reserved 73.
	volatile uint32_t RSVD_74;	 // 0x170 Reserved 74.
	volatile uint32_t RSVD_75;	 // 0x174 Reserved 75.
	volatile uint32_t RSVD_76;	 // 0x178 Reserved 76.
	volatile uint32_t RSVD_77;	 // 0x17c Reserved 77.
	volatile uint32_t RSVD_78;	 // 0x180 Reserved 78.
	volatile uint32_t RSVD_79;	 // 0x184 Reserved 79.
	volatile uint32_t RSVD_80;	 // 0x188 Reserved 80.
	volatile uint32_t RSVD_81;	 // 0x18c Reserved 81.
	volatile uint32_t RSVD_82;	 // 0x190 Reserved 82.
	volatile uint32_t RSVD_83;	 // 0x194 Reserved 83.
	volatile uint32_t RSVD_84;	 // 0x198 Reserved 84.
	volatile uint32_t RSVD_85;	 // 0x19c Reserved 85.
	volatile uint32_t RSVD_86;	 // 0x1a0 Reserved 86.
	volatile uint32_t RSVD_87;	 // 0x1a4 Reserved 87.
	volatile uint32_t RSVD_88;	 // 0x1a8 Reserved 88.
	volatile uint32_t RSVD_89;	 // 0x1ac Reserved 89.
	volatile uint32_t RSVD_90;	 // 0x1b0 Reserved 90.
	volatile uint32_t RSVD_91;	 // 0x1b4 Reserved 91.
	volatile uint32_t RSVD_92;	 // 0x1b8 Reserved 92.
	volatile uint32_t RSVD_93;	 // 0x1bc Reserved 93.
	volatile uint32_t RSVD_94;	 // 0x1c0 Reserved 94.
	volatile uint32_t RSVD_95;	 // 0x1c4 Reserved 95.
	volatile uint32_t RSVD_96;	 // 0x1c8 Reserved 96.
	volatile uint32_t RSVD_97;	 // 0x1cc Reserved 97.
	volatile uint32_t RSVD_98;	 // 0x1d0 Reserved 98.
	volatile uint32_t RSVD_99;	 // 0x1d4 Reserved 99.
	volatile uint32_t RSVD_100;	 // 0x1d8 Reserved 100.
	volatile uint32_t RSVD_101;	 // 0x1dc Reserved 101.
	volatile uint32_t RSVD_102;	 // 0x1e0 Reserved 102.
	volatile uint32_t RSVD_103;	 // 0x1e4 Reserved 103.
	volatile uint32_t RSVD_104;	 // 0x1e8 Reserved 104.
	volatile uint32_t RSVD_105;	 // 0x1ec Reserved 105.
	volatile uint32_t RSVD_106;	 // 0x1f0 Reserved 106.
	volatile uint32_t RSVD_107;	 // 0x1f4 Reserved 107.
	volatile uint32_t RSVD_108;	 // 0x1f8 Reserved 108.
	volatile uint32_t RSVD_109;	 // 0x1fc Reserved 109.
	volatile uint32_t RSVD_110;	 // 0x200 Reserved 110.
	volatile uint32_t RSVD_111;	 // 0x204 Reserved 111.
	volatile uint32_t RSVD_112;	 // 0x208 Reserved 112.
	volatile uint32_t RSVD_113;	 // 0x20c Reserved 113.
	volatile uint32_t RSVD_114;	 // 0x210 Reserved 114.
	volatile uint32_t RSVD_115;	 // 0x214 Reserved 115.
	volatile uint32_t RSVD_116;	 // 0x218 Reserved 116.
	volatile uint32_t RSVD_117;	 // 0x21c Reserved 117.
	volatile uint32_t RSVD_118;	 // 0x220 Reserved 118.
	volatile uint32_t RSVD_119;	 // 0x224 Reserved 119.
	volatile uint32_t RSVD_120;	 // 0x228 Reserved 120.
	volatile uint32_t RSVD_121;	 // 0x22c Reserved 121.
	volatile uint32_t RSVD_122;	 // 0x230 Reserved 122.
	volatile uint32_t RSVD_123;	 // 0x234 Reserved 123.
	volatile uint32_t RSVD_124;	 // 0x238 Reserved 124.
	volatile uint32_t RSVD_125;	 // 0x23c Reserved 125.
	volatile uint32_t RSVD_126;	 // 0x240 Reserved 126.
	volatile uint32_t RSVD_127;	 // 0x244 Reserved 127.
	volatile uint32_t RSVD_128;	 // 0x248 Reserved 128.
	volatile uint32_t RSVD_129;	 // 0x24c Reserved 129.
	volatile uint32_t RSVD_130;	 // 0x250 Reserved 130.
	volatile uint32_t RSVD_131;	 // 0x254 Reserved 131.
	volatile uint32_t RSVD_132;	 // 0x258 Reserved 132.
	volatile uint32_t RSVD_133;	 // 0x25c Reserved 133.
	volatile uint32_t RSVD_134;	 // 0x260 Reserved 134.
	volatile uint32_t RSVD_135;	 // 0x264 Reserved 135.
	volatile uint32_t RSVD_136;	 // 0x268 Reserved 136.
	volatile uint32_t RSVD_137;	 // 0x26c Reserved 137.
	volatile uint32_t RSVD_138;	 // 0x270 Reserved 138.
	volatile uint32_t RSVD_139;	 // 0x274 Reserved 139.
	volatile uint32_t RSVD_140;	 // 0x278 Reserved 140.
	volatile uint32_t RSVD_141;	 // 0x27c Reserved 141.
	volatile uint32_t RSVD_142;	 // 0x280 Reserved 142.
	volatile uint32_t RSVD_143;	 // 0x284 Reserved 143.
	volatile uint32_t RSVD_144;	 // 0x288 Reserved 144.
	volatile uint32_t RSVD_145;	 // 0x28c Reserved 145.
	volatile uint32_t RSVD_146;	 // 0x290 Reserved 146.
	volatile uint32_t RSVD_147;	 // 0x294 Reserved 147.
	volatile uint32_t RSVD_148;	 // 0x298 Reserved 148.
	volatile uint32_t RSVD_149;	 // 0x29c Reserved 149.
	volatile uint32_t RSVD_150;	 // 0x2a0 Reserved 150.
	volatile uint32_t RSVD_151;	 // 0x2a4 Reserved 151.
	volatile uint32_t RSVD_152;	 // 0x2a8 Reserved 152.
	volatile uint32_t RSVD_153;	 // 0x2ac Reserved 153.
	volatile uint32_t RSVD_154;	 // 0x2b0 Reserved 154.
	volatile uint32_t RSVD_155;	 // 0x2b4 Reserved 155.
	volatile uint32_t RSVD_156;	 // 0x2b8 Reserved 156.
	volatile uint32_t RSVD_157;	 // 0x2bc Reserved 157.
	volatile uint32_t RSVD_158;	 // 0x2c0 Reserved 158.
	volatile uint32_t RSVD_159;	 // 0x2c4 Reserved 159.
	volatile uint32_t RSVD_160;	 // 0x2c8 Reserved 160.
	volatile uint32_t RSVD_161;	 // 0x2cc Reserved 161.
	volatile uint32_t RSVD_162;	 // 0x2d0 Reserved 162.
	volatile uint32_t RSVD_163;	 // 0x2d4 Reserved 163.
	volatile uint32_t RSVD_164;	 // 0x2d8 Reserved 164.
	volatile uint32_t RSVD_165;	 // 0x2dc Reserved 165.
	volatile uint32_t RSVD_166;	 // 0x2e0 Reserved 166.
	volatile uint32_t RSVD_167;	 // 0x2e4 Reserved 167.
	volatile uint32_t RSVD_168;	 // 0x2e8 Reserved 168.
	volatile uint32_t RSVD_169;	 // 0x2ec Reserved 169.
	volatile uint32_t RSVD_170;	 // 0x2f0 Reserved 170.
	volatile uint32_t RSVD_171;	 // 0x2f4 Reserved 171.
	volatile uint32_t RSVD_172;	 // 0x2f8 Reserved 172.
	volatile uint32_t RSVD_173;	 // 0x2fc Reserved 173.
	volatile uint32_t RSVD_174;	 // 0x300 Reserved 174.
	volatile uint32_t RSVD_175;	 // 0x304 Reserved 175.
	volatile uint32_t RSVD_176;	 // 0x308 Reserved 176.
	volatile uint32_t RSVD_177;	 // 0x30c Reserved 177.
	volatile uint32_t RSVD_178;	 // 0x310 Reserved 178.
	volatile uint32_t RSVD_179;	 // 0x314 Reserved 179.
	volatile uint32_t RSVD_180;	 // 0x318 Reserved 180.
	volatile uint32_t RSVD_181;	 // 0x31c Reserved 181.
	volatile uint32_t RSVD_182;	 // 0x320 Reserved 182.
	volatile uint32_t RSVD_183;	 // 0x324 Reserved 183.
	volatile uint32_t RSVD_184;	 // 0x328 Reserved 184.
	volatile uint32_t RSVD_185;	 // 0x32c Reserved 185.
	volatile uint32_t RSVD_186;	 // 0x330 Reserved 186.
	volatile uint32_t RSVD_187;	 // 0x334 Reserved 187.
	volatile uint32_t RSVD_188;	 // 0x338 Reserved 188.
	volatile uint32_t RSVD_189;	 // 0x33c Reserved 189.
	volatile uint32_t RSVD_190;	 // 0x340 Reserved 190.
	volatile uint32_t RSVD_191;	 // 0x344 Reserved 191.
	volatile uint32_t RSVD_192;	 // 0x348 Reserved 192.
	volatile uint32_t RSVD_193;	 // 0x34c Reserved 193.
	volatile uint32_t RSVD_194;	 // 0x350 Reserved 194.
	volatile uint32_t RSVD_195;	 // 0x354 Reserved 195.
	volatile uint32_t RSVD_196;	 // 0x358 Reserved 196.
	volatile uint32_t RSVD_197;	 // 0x35c Reserved 197.
	volatile uint32_t RSVD_198;	 // 0x360 Reserved 198.
	volatile uint32_t RSVD_199;	 // 0x364 Reserved 199.
	volatile uint32_t RSVD_200;	 // 0x368 Reserved 200.
	volatile uint32_t RSVD_201;	 // 0x36c Reserved 201.
	volatile uint32_t RSVD_202;	 // 0x370 Reserved 202.
	volatile uint32_t RSVD_203;	 // 0x374 Reserved 203.
	volatile uint32_t RSVD_204;	 // 0x378 Reserved 204.
	volatile uint32_t RSVD_205;	 // 0x37c Reserved 205.
	volatile uint32_t RSVD_206;	 // 0x380 Reserved 206.
	volatile uint32_t RSVD_207;	 // 0x384 Reserved 207.
	volatile uint32_t RSVD_208;	 // 0x388 Reserved 208.
	volatile uint32_t RSVD_209;	 // 0x38c Reserved 209.
	volatile uint32_t RSVD_210;	 // 0x390 Reserved 210.
	volatile uint32_t RSVD_211;	 // 0x394 Reserved 211.
	volatile uint32_t RSVD_212;	 // 0x398 Reserved 212.
	volatile uint32_t RSVD_213;	 // 0x39c Reserved 213.
	volatile uint32_t RSVD_214;	 // 0x3a0 Reserved 214.
	volatile uint32_t RSVD_215;	 // 0x3a4 Reserved 215.
	volatile uint32_t RSVD_216;	 // 0x3a8 Reserved 216.
	volatile uint32_t RSVD_217;	 // 0x3ac Reserved 217.
	volatile uint32_t RSVD_218;	 // 0x3b0 Reserved 218.
	volatile uint32_t RSVD_219;	 // 0x3b4 Reserved 219.
	volatile uint32_t RSVD_220;	 // 0x3b8 Reserved 220.
	volatile uint32_t RSVD_221;	 // 0x3bc Reserved 221.
	volatile uint32_t RSVD_222;	 // 0x3c0 Reserved 222.
	volatile uint32_t RSVD_223;	 // 0x3c4 Reserved 223.
	volatile uint32_t RSVD_224;	 // 0x3c8 Reserved 224.
	volatile uint32_t RSVD_225;	 // 0x3cc Reserved 225.
	volatile uint32_t RSVD_226;	 // 0x3d0 Reserved 226.
	volatile uint32_t RSVD_227;	 // 0x3d4 Reserved 227.
	volatile uint32_t RSVD_228;	 // 0x3d8 Reserved 228.
	volatile uint32_t RSVD_229;	 // 0x3dc Reserved 229.
	volatile uint32_t RSVD_230;	 // 0x3e0 Reserved 230.
	volatile uint32_t RSVD_231;	 // 0x3e4 Reserved 231.
	volatile uint32_t RSVD_232;	 // 0x3e8 Reserved 232.
	volatile uint32_t RSVD_233;	 // 0x3ec Reserved 233.
	volatile uint32_t RSVD_234;	 // 0x3f0 Reserved 234.
	volatile uint32_t RSVD_235;	 // 0x3f4 Reserved 235.
	volatile uint32_t RSVD_236;	 // 0x3f8 Reserved 236.
	volatile uint32_t RSVD_237;	 // 0x3fc Reserved 237.
	volatile uint32_t RSVD_238;	 // 0x400 Reserved 238.
	volatile uint32_t RSVD_239;	 // 0x404 Reserved 239.
	volatile uint32_t RSVD_240;	 // 0x408 Reserved 240.
	volatile uint32_t RSVD_241;	 // 0x40c Reserved 241.
	volatile uint32_t RSVD_242;	 // 0x410 Reserved 242.
	volatile uint32_t RSVD_243;	 // 0x414 Reserved 243.
	volatile uint32_t RSVD_244;	 // 0x418 Reserved 244.
	volatile uint32_t RSVD_245;	 // 0x41c Reserved 245.
	volatile uint32_t RSVD_246;	 // 0x420 Reserved 246.
	volatile uint32_t RSVD_247;	 // 0x424 Reserved 247.
	volatile uint32_t RSVD_248;	 // 0x428 Reserved 248.
	volatile uint32_t RSVD_249;	 // 0x42c Reserved 249.
	volatile uint32_t RSVD_250;	 // 0x430 Reserved 250.
	volatile uint32_t RSVD_251;	 // 0x434 Reserved 251.
	volatile uint32_t RSVD_252;	 // 0x438 Reserved 252.
	volatile uint32_t RSVD_253;	 // 0x43c Reserved 253.
	volatile uint32_t RSVD_254;	 // 0x440 Reserved 254.
	volatile uint32_t RSVD_255;	 // 0x444 Reserved 255.
	volatile uint32_t RSVD_256;	 // 0x448 Reserved 256.
	volatile uint32_t RSVD_257;	 // 0x44c Reserved 257.
	volatile uint32_t RSVD_258;	 // 0x450 Reserved 258.
	volatile uint32_t RSVD_259;	 // 0x454 Reserved 259.
	volatile uint32_t RSVD_260;	 // 0x458 Reserved 260.
	volatile uint32_t RSVD_261;	 // 0x45c Reserved 261.
	volatile uint32_t RSVD_262;	 // 0x460 Reserved 262.
	volatile uint32_t RSVD_263;	 // 0x464 Reserved 263.
	volatile uint32_t RSVD_264;	 // 0x468 Reserved 264.
	volatile uint32_t RSVD_265;	 // 0x46c Reserved 265.
	volatile uint32_t RSVD_266;	 // 0x470 Reserved 266.
	volatile uint32_t RSVD_267;	 // 0x474 Reserved 267.
	volatile uint32_t RSVD_268;	 // 0x478 Reserved 268.
	volatile uint32_t RSVD_269;	 // 0x47c Reserved 269.
	volatile uint32_t RSVD_270;	 // 0x480 Reserved 270.
	volatile uint32_t RSVD_271;	 // 0x484 Reserved 271.
	volatile uint32_t RSVD_272;	 // 0x488 Reserved 272.
	volatile uint32_t RSVD_273;	 // 0x48c Reserved 273.
	volatile uint32_t RSVD_274;	 // 0x490 Reserved 274.
	volatile uint32_t RSVD_275;	 // 0x494 Reserved 275.
	volatile uint32_t RSVD_276;	 // 0x498 Reserved 276.
	volatile uint32_t RSVD_277;	 // 0x49c Reserved 277.
	volatile uint32_t RSVD_278;	 // 0x4a0 Reserved 278.
	volatile uint32_t RSVD_279;	 // 0x4a4 Reserved 279.
	volatile uint32_t RSVD_280;	 // 0x4a8 Reserved 280.
	volatile uint32_t RSVD_281;	 // 0x4ac Reserved 281.
	volatile uint32_t RSVD_282;	 // 0x4b0 Reserved 282.
	volatile uint32_t RSVD_283;	 // 0x4b4 Reserved 283.
	volatile uint32_t RSVD_284;	 // 0x4b8 Reserved 284.
	volatile uint32_t RSVD_285;	 // 0x4bc Reserved 285.
	volatile uint32_t RSVD_286;	 // 0x4c0 Reserved 286.
	volatile uint32_t RSVD_287;	 // 0x4c4 Reserved 287.
	volatile uint32_t RSVD_288;	 // 0x4c8 Reserved 288.
	volatile uint32_t RSVD_289;	 // 0x4cc Reserved 289.
	volatile uint32_t RSVD_290;	 // 0x4d0 Reserved 290.
	volatile uint32_t RSVD_291;	 // 0x4d4 Reserved 291.
	volatile uint32_t RSVD_292;	 // 0x4d8 Reserved 292.
	volatile uint32_t RSVD_293;	 // 0x4dc Reserved 293.
	volatile uint32_t RSVD_294;	 // 0x4e0 Reserved 294.
	volatile uint32_t RSVD_295;	 // 0x4e4 Reserved 295.
	volatile uint32_t RSVD_296;	 // 0x4e8 Reserved 296.
	volatile uint32_t RSVD_297;	 // 0x4ec Reserved 297.
	volatile uint32_t RSVD_298;	 // 0x4f0 Reserved 298.
	volatile uint32_t RSVD_299;	 // 0x4f4 Reserved 299.
	volatile uint32_t RSVD_300;	 // 0x4f8 Reserved 300.
	volatile uint32_t RSVD_301;	 // 0x4fc Reserved 301.
	volatile uint32_t RSVD_302;	 // 0x500 Reserved 302.
	volatile uint32_t RSVD_303;	 // 0x504 Reserved 303.
	volatile uint32_t RSVD_304;	 // 0x508 Reserved 304.
	volatile uint32_t RSVD_305;	 // 0x50c Reserved 305.
	volatile uint32_t RSVD_306;	 // 0x510 Reserved 306.
	volatile uint32_t RSVD_307;	 // 0x514 Reserved 307.
	volatile uint32_t RSVD_308;	 // 0x518 Reserved 308.
	volatile uint32_t RSVD_309;	 // 0x51c Reserved 309.
	volatile uint32_t RSVD_310;	 // 0x520 Reserved 310.
	volatile uint32_t RSVD_311;	 // 0x524 Reserved 311.
	volatile uint32_t RSVD_312;	 // 0x528 Reserved 312.
	volatile uint32_t RSVD_313;	 // 0x52c Reserved 313.
	volatile uint32_t RSVD_314;	 // 0x530 Reserved 314.
	volatile uint32_t RSVD_315;	 // 0x534 Reserved 315.
	volatile uint32_t RSVD_316;	 // 0x538 Reserved 316.
	volatile uint32_t RSVD_317;	 // 0x53c Reserved 317.
	volatile uint32_t RSVD_318;	 // 0x540 Reserved 318.
	volatile uint32_t RSVD_319;	 // 0x544 Reserved 319.
	volatile uint32_t RSVD_320;	 // 0x548 Reserved 320.
	volatile uint32_t RSVD_321;	 // 0x54c Reserved 321.
	volatile uint32_t RSVD_322;	 // 0x550 Reserved 322.
	volatile uint32_t RSVD_323;	 // 0x554 Reserved 323.
	volatile uint32_t RSVD_324;	 // 0x558 Reserved 324.
	volatile uint32_t RSVD_325;	 // 0x55c Reserved 325.
	volatile uint32_t RSVD_326;	 // 0x560 Reserved 326.
	volatile uint32_t RSVD_327;	 // 0x564 Reserved 327.
	volatile uint32_t RSVD_328;	 // 0x568 Reserved 328.
	volatile uint32_t RSVD_329;	 // 0x56c Reserved 329.
	volatile uint32_t RSVD_330;	 // 0x570 Reserved 330.
	volatile uint32_t RSVD_331;	 // 0x574 Reserved 331.
	volatile uint32_t RSVD_332;	 // 0x578 Reserved 332.
	volatile uint32_t RSVD_333;	 // 0x57c Reserved 333.
	volatile uint32_t RSVD_334;	 // 0x580 Reserved 334.
	volatile uint32_t RSVD_335;	 // 0x584 Reserved 335.
	volatile uint32_t RSVD_336;	 // 0x588 Reserved 336.
	volatile uint32_t RSVD_337;	 // 0x58c Reserved 337.
	volatile uint32_t RSVD_338;	 // 0x590 Reserved 338.
	volatile uint32_t RSVD_339;	 // 0x594 Reserved 339.
	volatile uint32_t RSVD_340;	 // 0x598 Reserved 340.
	volatile uint32_t RSVD_341;	 // 0x59c Reserved 341.
	volatile uint32_t RSVD_342;	 // 0x5a0 Reserved 342.
	volatile uint32_t RSVD_343;	 // 0x5a4 Reserved 343.
	volatile uint32_t RSVD_344;	 // 0x5a8 Reserved 344.
	volatile uint32_t RSVD_345;	 // 0x5ac Reserved 345.
	volatile uint32_t RSVD_346;	 // 0x5b0 Reserved 346.
	volatile uint32_t RSVD_347;	 // 0x5b4 Reserved 347.
	volatile uint32_t RSVD_348;	 // 0x5b8 Reserved 348.
	volatile uint32_t RSVD_349;	 // 0x5bc Reserved 349.
	volatile uint32_t RSVD_350;	 // 0x5c0 Reserved 350.
	volatile uint32_t RSVD_351;	 // 0x5c4 Reserved 351.
	volatile uint32_t RSVD_352;	 // 0x5c8 Reserved 352.
	volatile uint32_t RSVD_353;	 // 0x5cc Reserved 353.
	volatile uint32_t RSVD_354;	 // 0x5d0 Reserved 354.
	volatile uint32_t RSVD_355;	 // 0x5d4 Reserved 355.
	volatile uint32_t RSVD_356;	 // 0x5d8 Reserved 356.
	volatile uint32_t RSVD_357;	 // 0x5dc Reserved 357.
	volatile uint32_t RSVD_358;	 // 0x5e0 Reserved 358.
	volatile uint32_t RSVD_359;	 // 0x5e4 Reserved 359.
	volatile uint32_t RSVD_360;	 // 0x5e8 Reserved 360.
	volatile uint32_t RSVD_361;	 // 0x5ec Reserved 361.
	volatile uint32_t RSVD_362;	 // 0x5f0 Reserved 362.
	volatile uint32_t RSVD_363;	 // 0x5f4 Reserved 363.
	volatile uint32_t RSVD_364;	 // 0x5f8 Reserved 364.
	volatile uint32_t RSVD_365;	 // 0x5fc Reserved 365.
	volatile uint32_t RSVD_366;	 // 0x600 Reserved 366.
	volatile uint32_t RSVD_367;	 // 0x604 Reserved 367.
	volatile uint32_t RSVD_368;	 // 0x608 Reserved 368.
	volatile uint32_t RSVD_369;	 // 0x60c Reserved 369.
	volatile uint32_t RSVD_370;	 // 0x610 Reserved 370.
	volatile uint32_t RSVD_371;	 // 0x614 Reserved 371.
	volatile uint32_t RSVD_372;	 // 0x618 Reserved 372.
	volatile uint32_t RSVD_373;	 // 0x61c Reserved 373.
	volatile uint32_t RSVD_374;	 // 0x620 Reserved 374.
	volatile uint32_t RSVD_375;	 // 0x624 Reserved 375.
	volatile uint32_t RSVD_376;	 // 0x628 Reserved 376.
	volatile uint32_t RSVD_377;	 // 0x62c Reserved 377.
	volatile uint32_t RSVD_378;	 // 0x630 Reserved 378.
	volatile uint32_t RSVD_379;	 // 0x634 Reserved 379.
	volatile uint32_t RSVD_380;	 // 0x638 Reserved 380.
	volatile uint32_t RSVD_381;	 // 0x63c Reserved 381.
	volatile uint32_t RSVD_382;	 // 0x640 Reserved 382.
	volatile uint32_t RSVD_383;	 // 0x644 Reserved 383.
	volatile uint32_t RSVD_384;	 // 0x648 Reserved 384.
	volatile uint32_t RSVD_385;	 // 0x64c Reserved 385.
	volatile uint32_t RSVD_386;	 // 0x650 Reserved 386.
	volatile uint32_t RSVD_387;	 // 0x654 Reserved 387.
	volatile uint32_t RSVD_388;	 // 0x658 Reserved 388.
	volatile uint32_t RSVD_389;	 // 0x65c Reserved 389.
	volatile uint32_t RSVD_390;	 // 0x660 Reserved 390.
	volatile uint32_t RSVD_391;	 // 0x664 Reserved 391.
	volatile uint32_t RSVD_392;	 // 0x668 Reserved 392.
	volatile uint32_t RSVD_393;	 // 0x66c Reserved 393.
	volatile uint32_t RSVD_394;	 // 0x670 Reserved 394.
	volatile uint32_t RSVD_395;	 // 0x674 Reserved 395.
	volatile uint32_t RSVD_396;	 // 0x678 Reserved 396.
	volatile uint32_t RSVD_397;	 // 0x67c Reserved 397.
	volatile uint32_t RSVD_398;	 // 0x680 Reserved 398.
	volatile uint32_t RSVD_399;	 // 0x684 Reserved 399.
	volatile uint32_t RSVD_400;	 // 0x688 Reserved 400.
	volatile uint32_t RSVD_401;	 // 0x68c Reserved 401.
	volatile uint32_t RSVD_402;	 // 0x690 Reserved 402.
	volatile uint32_t RSVD_403;	 // 0x694 Reserved 403.
	volatile uint32_t RSVD_404;	 // 0x698 Reserved 404.
	volatile uint32_t RSVD_405;	 // 0x69c Reserved 405.
	volatile uint32_t RSVD_406;	 // 0x6a0 Reserved 406.
	volatile uint32_t RSVD_407;	 // 0x6a4 Reserved 407.
	volatile uint32_t RSVD_408;	 // 0x6a8 Reserved 408.
	volatile uint32_t RSVD_409;	 // 0x6ac Reserved 409.
	volatile uint32_t RSVD_410;	 // 0x6b0 Reserved 410.
	volatile uint32_t RSVD_411;	 // 0x6b4 Reserved 411.
	volatile uint32_t RSVD_412;	 // 0x6b8 Reserved 412.
	volatile uint32_t RSVD_413;	 // 0x6bc Reserved 413.
	volatile uint32_t RSVD_414;	 // 0x6c0 Reserved 414.
	volatile uint32_t RSVD_415;	 // 0x6c4 Reserved 415.
	volatile uint32_t RSVD_416;	 // 0x6c8 Reserved 416.
	volatile uint32_t RSVD_417;	 // 0x6cc Reserved 417.
	volatile uint32_t RSVD_418;	 // 0x6d0 Reserved 418.
	volatile uint32_t RSVD_419;	 // 0x6d4 Reserved 419.
	volatile uint32_t RSVD_420;	 // 0x6d8 Reserved 420.
	volatile uint32_t RSVD_421;	 // 0x6dc Reserved 421.
	volatile uint32_t RSVD_422;	 // 0x6e0 Reserved 422.
	volatile uint32_t RSVD_423;	 // 0x6e4 Reserved 423.
	volatile uint32_t RSVD_424;	 // 0x6e8 Reserved 424.
	volatile uint32_t RSVD_425;	 // 0x6ec Reserved 425.
	volatile uint32_t RSVD_426;	 // 0x6f0 Reserved 426.
	volatile uint32_t RSVD_427;	 // 0x6f4 Reserved 427.
	volatile uint32_t RSVD_428;	 // 0x6f8 Reserved 428.
	volatile uint32_t RSVD_429;	 // 0x6fc Reserved 429.
	volatile uint32_t RSVD_430;	 // 0x700 Reserved 430.
	volatile uint32_t RSVD_431;	 // 0x704 Reserved 431.
	volatile uint32_t RSVD_432;	 // 0x708 Reserved 432.
	volatile uint32_t RSVD_433;	 // 0x70c Reserved 433.
	volatile uint32_t RSVD_434;	 // 0x710 Reserved 434.
	volatile uint32_t RSVD_435;	 // 0x714 Reserved 435.
	volatile uint32_t RSVD_436;	 // 0x718 Reserved 436.
	volatile uint32_t RSVD_437;	 // 0x71c Reserved 437.
	volatile uint32_t RSVD_438;	 // 0x720 Reserved 438.
	volatile uint32_t RSVD_439;	 // 0x724 Reserved 439.
	volatile uint32_t RSVD_440;	 // 0x728 Reserved 440.
	volatile uint32_t RSVD_441;	 // 0x72c Reserved 441.
	volatile uint32_t RSVD_442;	 // 0x730 Reserved 442.
	volatile uint32_t RSVD_443;	 // 0x734 Reserved 443.
	volatile uint32_t RSVD_444;	 // 0x738 Reserved 444.
	volatile uint32_t RSVD_445;	 // 0x73c Reserved 445.
	volatile uint32_t RSVD_446;	 // 0x740 Reserved 446.
	volatile uint32_t RSVD_447;	 // 0x744 Reserved 447.
	volatile uint32_t RSVD_448;	 // 0x748 Reserved 448.
	volatile uint32_t RSVD_449;	 // 0x74c Reserved 449.
	volatile uint32_t RSVD_450;	 // 0x750 Reserved 450.
	volatile uint32_t RSVD_451;	 // 0x754 Reserved 451.
	volatile uint32_t RSVD_452;	 // 0x758 Reserved 452.
	volatile uint32_t RSVD_453;	 // 0x75c Reserved 453.
	volatile uint32_t RSVD_454;	 // 0x760 Reserved 454.
	volatile uint32_t RSVD_455;	 // 0x764 Reserved 455.
	volatile uint32_t RSVD_456;	 // 0x768 Reserved 456.
	volatile uint32_t RSVD_457;	 // 0x76c Reserved 457.
	volatile uint32_t RSVD_458;	 // 0x770 Reserved 458.
	volatile uint32_t RSVD_459;	 // 0x774 Reserved 459.
	volatile uint32_t RSVD_460;	 // 0x778 Reserved 460.
	volatile uint32_t RSVD_461;	 // 0x77c Reserved 461.
	volatile uint32_t RSVD_462;	 // 0x780 Reserved 462.
	volatile uint32_t RSVD_463;	 // 0x784 Reserved 463.
	volatile uint32_t RSVD_464;	 // 0x788 Reserved 464.
	volatile uint32_t RSVD_465;	 // 0x78c Reserved 465.
	volatile uint32_t RSVD_466;	 // 0x790 Reserved 466.
	volatile uint32_t RSVD_467;	 // 0x794 Reserved 467.
	volatile uint32_t RSVD_468;	 // 0x798 Reserved 468.
	volatile uint32_t RSVD_469;	 // 0x79c Reserved 469.
	volatile uint32_t RSVD_470;	 // 0x7a0 Reserved 470.
	volatile uint32_t RSVD_471;	 // 0x7a4 Reserved 471.
	volatile uint32_t RSVD_472;	 // 0x7a8 Reserved 472.
	volatile uint32_t RSVD_473;	 // 0x7ac Reserved 473.
	volatile uint32_t RSVD_474;	 // 0x7b0 Reserved 474.
	volatile uint32_t RSVD_475;	 // 0x7b4 Reserved 475.
	volatile uint32_t RSVD_476;	 // 0x7b8 Reserved 476.
	volatile uint32_t RSVD_477;	 // 0x7bc Reserved 477.
	volatile uint32_t RSVD_478;	 // 0x7c0 Reserved 478.
	volatile uint32_t RSVD_479;	 // 0x7c4 Reserved 479.
	volatile uint32_t RSVD_480;	 // 0x7c8 Reserved 480.
	volatile uint32_t RSVD_481;	 // 0x7cc Reserved 481.
	volatile uint32_t RSVD_482;	 // 0x7d0 Reserved 482.
	volatile uint32_t RSVD_483;	 // 0x7d4 Reserved 483.
	volatile uint32_t RSVD_484;	 // 0x7d8 Reserved 484.
	volatile uint32_t RSVD_485;	 // 0x7dc Reserved 485.
	volatile uint32_t RSVD_486;	 // 0x7e0 Reserved 486.
	volatile uint32_t RSVD_487;	 // 0x7e4 Reserved 487.
	volatile uint32_t RSVD_488;	 // 0x7e8 Reserved 488.
	volatile uint32_t RSVD_489;	 // 0x7ec Reserved 489.
	volatile uint32_t RSVD_490;	 // 0x7f0 Reserved 490.
	volatile uint32_t RSVD_491;	 // 0x7f4 Reserved 491.
	volatile uint32_t RSVD_492;	 // 0x7f8 Reserved 492.
	volatile uint32_t RSVD_493;	 // 0x7fc Reserved 493.
	volatile uint32_t RSVD_494;	 // 0x800 Reserved 494.
	volatile uint32_t RSVD_495;	 // 0x804 Reserved 495.
	volatile uint32_t RSVD_496;	 // 0x808 Reserved 496.
	volatile uint32_t RSVD_497;	 // 0x80c Reserved 497.
	volatile uint32_t RSVD_498;	 // 0x810 Reserved 498.
	volatile uint32_t RSVD_499;	 // 0x814 Reserved 499.
	volatile uint32_t RSVD_500;	 // 0x818 Reserved 500.
	volatile uint32_t RSVD_501;	 // 0x81c Reserved 501.
	volatile uint32_t RSVD_502;	 // 0x820 Reserved 502.
	volatile uint32_t RSVD_503;	 // 0x824 Reserved 503.
	volatile uint32_t RSVD_504;	 // 0x828 Reserved 504.
	volatile uint32_t RSVD_505;	 // 0x82c Reserved 505.
	volatile uint32_t RSVD_506;	 // 0x830 Reserved 506.
	volatile uint32_t RSVD_507;	 // 0x834 Reserved 507.
	volatile uint32_t RSVD_508;	 // 0x838 Reserved 508.
	volatile uint32_t RSVD_509;	 // 0x83c Reserved 509.
	volatile uint32_t RSVD_510;	 // 0x840 Reserved 510.
	volatile uint32_t RSVD_511;	 // 0x844 Reserved 511.
	volatile uint32_t RSVD_512;	 // 0x848 Reserved 512.
	volatile uint32_t RSVD_513;	 // 0x84c Reserved 513.
	volatile uint32_t RSVD_514;	 // 0x850 Reserved 514.
	volatile uint32_t RSVD_515;	 // 0x854 Reserved 515.
	volatile uint32_t RSVD_516;	 // 0x858 Reserved 516.
	volatile uint32_t RSVD_517;	 // 0x85c Reserved 517.
	volatile uint32_t RSVD_518;	 // 0x860 Reserved 518.
	volatile uint32_t RSVD_519;	 // 0x864 Reserved 519.
	volatile uint32_t RSVD_520;	 // 0x868 Reserved 520.
	volatile uint32_t RSVD_521;	 // 0x86c Reserved 521.
	volatile uint32_t RSVD_522;	 // 0x870 Reserved 522.
	volatile uint32_t RSVD_523;	 // 0x874 Reserved 523.
	volatile uint32_t RSVD_524;	 // 0x878 Reserved 524.
	volatile uint32_t RSVD_525;	 // 0x87c Reserved 525.
	volatile uint32_t RSVD_526;	 // 0x880 Reserved 526.
	volatile uint32_t RSVD_527;	 // 0x884 Reserved 527.
	volatile uint32_t RSVD_528;	 // 0x888 Reserved 528.
	volatile uint32_t RSVD_529;	 // 0x88c Reserved 529.
	volatile uint32_t RSVD_530;	 // 0x890 Reserved 530.
	volatile uint32_t RSVD_531;	 // 0x894 Reserved 531.
	volatile uint32_t RSVD_532;	 // 0x898 Reserved 532.
	volatile uint32_t RSVD_533;	 // 0x89c Reserved 533.
	volatile uint32_t RSVD_534;	 // 0x8a0 Reserved 534.
	volatile uint32_t RSVD_535;	 // 0x8a4 Reserved 535.
	volatile uint32_t RSVD_536;	 // 0x8a8 Reserved 536.
	volatile uint32_t RSVD_537;	 // 0x8ac Reserved 537.
	volatile uint32_t RSVD_538;	 // 0x8b0 Reserved 538.
	volatile uint32_t RSVD_539;	 // 0x8b4 Reserved 539.
	volatile uint32_t RSVD_540;	 // 0x8b8 Reserved 540.
	volatile uint32_t RSVD_541;	 // 0x8bc Reserved 541.
	volatile uint32_t RSVD_542;	 // 0x8c0 Reserved 542.
	volatile uint32_t RSVD_543;	 // 0x8c4 Reserved 543.
	volatile uint32_t RSVD_544;	 // 0x8c8 Reserved 544.
	volatile uint32_t RSVD_545;	 // 0x8cc Reserved 545.
	volatile uint32_t RSVD_546;	 // 0x8d0 Reserved 546.
	volatile uint32_t RSVD_547;	 // 0x8d4 Reserved 547.
	volatile uint32_t RSVD_548;	 // 0x8d8 Reserved 548.
	volatile uint32_t RSVD_549;	 // 0x8dc Reserved 549.
	volatile uint32_t RSVD_550;	 // 0x8e0 Reserved 550.
	volatile uint32_t RSVD_551;	 // 0x8e4 Reserved 551.
	volatile uint32_t RSVD_552;	 // 0x8e8 Reserved 552.
	volatile uint32_t RSVD_553;	 // 0x8ec Reserved 553.
	volatile uint32_t RSVD_554;	 // 0x8f0 Reserved 554.
	volatile uint32_t RSVD_555;	 // 0x8f4 Reserved 555.
	volatile uint32_t RSVD_556;	 // 0x8f8 Reserved 556.
	volatile uint32_t RSVD_557;	 // 0x8fc Reserved 557.
	volatile uint32_t RSVD_558;	 // 0x900 Reserved 558.
	volatile uint32_t RSVD_559;	 // 0x904 Reserved 559.
	volatile uint32_t RSVD_560;	 // 0x908 Reserved 560.
	volatile uint32_t RSVD_561;	 // 0x90c Reserved 561.
	volatile uint32_t RSVD_562;	 // 0x910 Reserved 562.
	volatile uint32_t RSVD_563;	 // 0x914 Reserved 563.
	volatile uint32_t RSVD_564;	 // 0x918 Reserved 564.
	volatile uint32_t RSVD_565;	 // 0x91c Reserved 565.
	volatile uint32_t RSVD_566;	 // 0x920 Reserved 566.
	volatile uint32_t RSVD_567;	 // 0x924 Reserved 567.
	volatile uint32_t RSVD_568;	 // 0x928 Reserved 568.
	volatile uint32_t RSVD_569;	 // 0x92c Reserved 569.
	volatile uint32_t RSVD_570;	 // 0x930 Reserved 570.
	volatile uint32_t RSVD_571;	 // 0x934 Reserved 571.
	volatile uint32_t RSVD_572;	 // 0x938 Reserved 572.
	volatile uint32_t RSVD_573;	 // 0x93c Reserved 573.
	volatile uint32_t RSVD_574;	 // 0x940 Reserved 574.
	volatile uint32_t RSVD_575;	 // 0x944 Reserved 575.
	volatile uint32_t RSVD_576;	 // 0x948 Reserved 576.
	volatile uint32_t RSVD_577;	 // 0x94c Reserved 577.
	volatile uint32_t RSVD_578;	 // 0x950 Reserved 578.
	volatile uint32_t RSVD_579;	 // 0x954 Reserved 579.
	volatile uint32_t RSVD_580;	 // 0x958 Reserved 580.
	volatile uint32_t RSVD_581;	 // 0x95c Reserved 581.
	volatile uint32_t RSVD_582;	 // 0x960 Reserved 582.
	volatile uint32_t RSVD_583;	 // 0x964 Reserved 583.
	volatile uint32_t RSVD_584;	 // 0x968 Reserved 584.
	volatile uint32_t RSVD_585;	 // 0x96c Reserved 585.
	volatile uint32_t RSVD_586;	 // 0x970 Reserved 586.
	volatile uint32_t RSVD_587;	 // 0x974 Reserved 587.
	volatile uint32_t RSVD_588;	 // 0x978 Reserved 588.
	volatile uint32_t RSVD_589;	 // 0x97c Reserved 589.
	volatile uint32_t RSVD_590;	 // 0x980 Reserved 590.
	volatile uint32_t RSVD_591;	 // 0x984 Reserved 591.
	volatile uint32_t RSVD_592;	 // 0x988 Reserved 592.
	volatile uint32_t RSVD_593;	 // 0x98c Reserved 593.
	volatile uint32_t RSVD_594;	 // 0x990 Reserved 594.
	volatile uint32_t RSVD_595;	 // 0x994 Reserved 595.
	volatile uint32_t RSVD_596;	 // 0x998 Reserved 596.
	volatile uint32_t RSVD_597;	 // 0x99c Reserved 597.
	volatile uint32_t RSVD_598;	 // 0x9a0 Reserved 598.
	volatile uint32_t RSVD_599;	 // 0x9a4 Reserved 599.
	volatile uint32_t RSVD_600;	 // 0x9a8 Reserved 600.
	volatile uint32_t RSVD_601;	 // 0x9ac Reserved 601.
	volatile uint32_t RSVD_602;	 // 0x9b0 Reserved 602.
	volatile uint32_t RSVD_603;	 // 0x9b4 Reserved 603.
	volatile uint32_t RSVD_604;	 // 0x9b8 Reserved 604.
	volatile uint32_t RSVD_605;	 // 0x9bc Reserved 605.
	volatile uint32_t RSVD_606;	 // 0x9c0 Reserved 606.
	volatile uint32_t RSVD_607;	 // 0x9c4 Reserved 607.
	volatile uint32_t RSVD_608;	 // 0x9c8 Reserved 608.
	volatile uint32_t RSVD_609;	 // 0x9cc Reserved 609.
	volatile uint32_t RSVD_610;	 // 0x9d0 Reserved 610.
	volatile uint32_t RSVD_611;	 // 0x9d4 Reserved 611.
	volatile uint32_t RSVD_612;	 // 0x9d8 Reserved 612.
	volatile uint32_t RSVD_613;	 // 0x9dc Reserved 613.
	volatile uint32_t RSVD_614;	 // 0x9e0 Reserved 614.
	volatile uint32_t RSVD_615;	 // 0x9e4 Reserved 615.
	volatile uint32_t RSVD_616;	 // 0x9e8 Reserved 616.
	volatile uint32_t RSVD_617;	 // 0x9ec Reserved 617.
	volatile uint32_t RSVD_618;	 // 0x9f0 Reserved 618.
	volatile uint32_t RSVD_619;	 // 0x9f4 Reserved 619.
	volatile uint32_t RSVD_620;	 // 0x9f8 Reserved 620.
	volatile uint32_t RSVD_621;	 // 0x9fc Reserved 621.
	volatile uint32_t RSVD_622;	 // 0xa00 Reserved 622.
	volatile uint32_t RSVD_623;	 // 0xa04 Reserved 623.
	volatile uint32_t RSVD_624;	 // 0xa08 Reserved 624.
	volatile uint32_t RSVD_625;	 // 0xa0c Reserved 625.
	volatile uint32_t RSVD_626;	 // 0xa10 Reserved 626.
	volatile uint32_t RSVD_627;	 // 0xa14 Reserved 627.
	volatile uint32_t RSVD_628;	 // 0xa18 Reserved 628.
	volatile uint32_t RSVD_629;	 // 0xa1c Reserved 629.
	volatile uint32_t RSVD_630;	 // 0xa20 Reserved 630.
	volatile uint32_t RSVD_631;	 // 0xa24 Reserved 631.
	volatile uint32_t RSVD_632;	 // 0xa28 Reserved 632.
	volatile uint32_t RSVD_633;	 // 0xa2c Reserved 633.
	volatile uint32_t RSVD_634;	 // 0xa30 Reserved 634.
	volatile uint32_t RSVD_635;	 // 0xa34 Reserved 635.
	volatile uint32_t RSVD_636;	 // 0xa38 Reserved 636.
	volatile uint32_t RSVD_637;	 // 0xa3c Reserved 637.
	volatile uint32_t RSVD_638;	 // 0xa40 Reserved 638.
	volatile uint32_t RSVD_639;	 // 0xa44 Reserved 639.
	volatile uint32_t RSVD_640;	 // 0xa48 Reserved 640.
	volatile uint32_t RSVD_641;	 // 0xa4c Reserved 641.
	volatile uint32_t RSVD_642;	 // 0xa50 Reserved 642.
	volatile uint32_t RSVD_643;	 // 0xa54 Reserved 643.
	volatile uint32_t RSVD_644;	 // 0xa58 Reserved 644.
	volatile uint32_t RSVD_645;	 // 0xa5c Reserved 645.
	volatile uint32_t RSVD_646;	 // 0xa60 Reserved 646.
	volatile uint32_t RSVD_647;	 // 0xa64 Reserved 647.
	volatile uint32_t RSVD_648;	 // 0xa68 Reserved 648.
	volatile uint32_t RSVD_649;	 // 0xa6c Reserved 649.
	volatile uint32_t RSVD_650;	 // 0xa70 Reserved 650.
	volatile uint32_t RSVD_651;	 // 0xa74 Reserved 651.
	volatile uint32_t RSVD_652;	 // 0xa78 Reserved 652.
	volatile uint32_t RSVD_653;	 // 0xa7c Reserved 653.
	volatile uint32_t RSVD_654;	 // 0xa80 Reserved 654.
	volatile uint32_t RSVD_655;	 // 0xa84 Reserved 655.
	volatile uint32_t RSVD_656;	 // 0xa88 Reserved 656.
	volatile uint32_t RSVD_657;	 // 0xa8c Reserved 657.
	volatile uint32_t RSVD_658;	 // 0xa90 Reserved 658.
	volatile uint32_t RSVD_659;	 // 0xa94 Reserved 659.
	volatile uint32_t RSVD_660;	 // 0xa98 Reserved 660.
	volatile uint32_t RSVD_661;	 // 0xa9c Reserved 661.
	volatile uint32_t RSVD_662;	 // 0xaa0 Reserved 662.
	volatile uint32_t RSVD_663;	 // 0xaa4 Reserved 663.
	volatile uint32_t RSVD_664;	 // 0xaa8 Reserved 664.
	volatile uint32_t RSVD_665;	 // 0xaac Reserved 665.
	volatile uint32_t RSVD_666;	 // 0xab0 Reserved 666.
	volatile uint32_t RSVD_667;	 // 0xab4 Reserved 667.
	volatile uint32_t RSVD_668;	 // 0xab8 Reserved 668.
	volatile uint32_t RSVD_669;	 // 0xabc Reserved 669.
	volatile uint32_t RSVD_670;	 // 0xac0 Reserved 670.
	volatile uint32_t RSVD_671;	 // 0xac4 Reserved 671.
	volatile uint32_t RSVD_672;	 // 0xac8 Reserved 672.
	volatile uint32_t RSVD_673;	 // 0xacc Reserved 673.
	volatile uint32_t RSVD_674;	 // 0xad0 Reserved 674.
	volatile uint32_t RSVD_675;	 // 0xad4 Reserved 675.
	volatile uint32_t RSVD_676;	 // 0xad8 Reserved 676.
	volatile uint32_t RSVD_677;	 // 0xadc Reserved 677.
	volatile uint32_t RSVD_678;	 // 0xae0 Reserved 678.
	volatile uint32_t RSVD_679;	 // 0xae4 Reserved 679.
	volatile uint32_t RSVD_680;	 // 0xae8 Reserved 680.
	volatile uint32_t RSVD_681;	 // 0xaec Reserved 681.
	volatile uint32_t RSVD_682;	 // 0xaf0 Reserved 682.
	volatile uint32_t RSVD_683;	 // 0xaf4 Reserved 683.
	volatile uint32_t RSVD_684;	 // 0xaf8 Reserved 684.
	volatile uint32_t RSVD_685;	 // 0xafc Reserved 685.
	volatile uint32_t RSVD_686;	 // 0xb00 Reserved 686.
	volatile uint32_t RSVD_687;	 // 0xb04 Reserved 687.
	volatile uint32_t RSVD_688;	 // 0xb08 Reserved 688.
	volatile uint32_t RSVD_689;	 // 0xb0c Reserved 689.
	volatile uint32_t RSVD_690;	 // 0xb10 Reserved 690.
	volatile uint32_t RSVD_691;	 // 0xb14 Reserved 691.
	volatile uint32_t RSVD_692;	 // 0xb18 Reserved 692.
	volatile uint32_t RSVD_693;	 // 0xb1c Reserved 693.
	volatile uint32_t RSVD_694;	 // 0xb20 Reserved 694.
	volatile uint32_t RSVD_695;	 // 0xb24 Reserved 695.
	volatile uint32_t RSVD_696;	 // 0xb28 Reserved 696.
	volatile uint32_t RSVD_697;	 // 0xb2c Reserved 697.
	volatile uint32_t RSVD_698;	 // 0xb30 Reserved 698.
	volatile uint32_t RSVD_699;	 // 0xb34 Reserved 699.
	volatile uint32_t RSVD_700;	 // 0xb38 Reserved 700.
	volatile uint32_t RSVD_701;	 // 0xb3c Reserved 701.
	volatile uint32_t RSVD_702;	 // 0xb40 Reserved 702.
	volatile uint32_t RSVD_703;	 // 0xb44 Reserved 703.
	volatile uint32_t RSVD_704;	 // 0xb48 Reserved 704.
	volatile uint32_t RSVD_705;	 // 0xb4c Reserved 705.
	volatile uint32_t RSVD_706;	 // 0xb50 Reserved 706.
	volatile uint32_t RSVD_707;	 // 0xb54 Reserved 707.
	volatile uint32_t RSVD_708;	 // 0xb58 Reserved 708.
	volatile uint32_t RSVD_709;	 // 0xb5c Reserved 709.
	volatile uint32_t RSVD_710;	 // 0xb60 Reserved 710.
	volatile uint32_t RSVD_711;	 // 0xb64 Reserved 711.
	volatile uint32_t RSVD_712;	 // 0xb68 Reserved 712.
	volatile uint32_t RSVD_713;	 // 0xb6c Reserved 713.
	volatile uint32_t RSVD_714;	 // 0xb70 Reserved 714.
	volatile uint32_t RSVD_715;	 // 0xb74 Reserved 715.
	volatile uint32_t RSVD_716;	 // 0xb78 Reserved 716.
	volatile uint32_t RSVD_717;	 // 0xb7c Reserved 717.
	volatile uint32_t RSVD_718;	 // 0xb80 Reserved 718.
	volatile uint32_t RSVD_719;	 // 0xb84 Reserved 719.
	volatile uint32_t RSVD_720;	 // 0xb88 Reserved 720.
	volatile uint32_t RSVD_721;	 // 0xb8c Reserved 721.
	volatile uint32_t RSVD_722;	 // 0xb90 Reserved 722.
	volatile uint32_t RSVD_723;	 // 0xb94 Reserved 723.
	volatile uint32_t RSVD_724;	 // 0xb98 Reserved 724.
	volatile uint32_t RSVD_725;	 // 0xb9c Reserved 725.
	volatile uint32_t RSVD_726;	 // 0xba0 Reserved 726.
	volatile uint32_t RSVD_727;	 // 0xba4 Reserved 727.
	volatile uint32_t RSVD_728;	 // 0xba8 Reserved 728.
	volatile uint32_t RSVD_729;	 // 0xbac Reserved 729.
	volatile uint32_t RSVD_730;	 // 0xbb0 Reserved 730.
	volatile uint32_t RSVD_731;	 // 0xbb4 Reserved 731.
	volatile uint32_t RSVD_732;	 // 0xbb8 Reserved 732.
	volatile uint32_t RSVD_733;	 // 0xbbc Reserved 733.
	volatile uint32_t RSVD_734;	 // 0xbc0 Reserved 734.
	volatile uint32_t RSVD_735;	 // 0xbc4 Reserved 735.
	volatile uint32_t RSVD_736;	 // 0xbc8 Reserved 736.
	volatile uint32_t RSVD_737;	 // 0xbcc Reserved 737.
	volatile uint32_t RSVD_738;	 // 0xbd0 Reserved 738.
	volatile uint32_t RSVD_739;	 // 0xbd4 Reserved 739.
	volatile uint32_t RSVD_740;	 // 0xbd8 Reserved 740.
	volatile uint32_t RSVD_741;	 // 0xbdc Reserved 741.
	volatile uint32_t RSVD_742;	 // 0xbe0 Reserved 742.
	volatile uint32_t RSVD_743;	 // 0xbe4 Reserved 743.
	volatile uint32_t RSVD_744;	 // 0xbe8 Reserved 744.
	volatile uint32_t RSVD_745;	 // 0xbec Reserved 745.
	volatile uint32_t RSVD_746;	 // 0xbf0 Reserved 746.
	volatile uint32_t RSVD_747;	 // 0xbf4 Reserved 747.
	volatile uint32_t RSVD_748;	 // 0xbf8 Reserved 748.
	volatile uint32_t RSVD_749;	 // 0xbfc Reserved 749.
	volatile uint32_t RSVD_750;	 // 0xc00 Reserved 750.
	volatile uint32_t RSVD_751;	 // 0xc04 Reserved 751.
	volatile uint32_t RSVD_752;	 // 0xc08 Reserved 752.
	volatile uint32_t RSVD_753;	 // 0xc0c Reserved 753.
	volatile uint32_t RSVD_754;	 // 0xc10 Reserved 754.
	volatile uint32_t RSVD_755;	 // 0xc14 Reserved 755.
	volatile uint32_t RSVD_756;	 // 0xc18 Reserved 756.
	volatile uint32_t RSVD_757;	 // 0xc1c Reserved 757.
	volatile uint32_t RSVD_758;	 // 0xc20 Reserved 758.
	volatile uint32_t RSVD_759;	 // 0xc24 Reserved 759.
	volatile uint32_t RSVD_760;	 // 0xc28 Reserved 760.
	volatile uint32_t RSVD_761;	 // 0xc2c Reserved 761.
	volatile uint32_t RSVD_762;	 // 0xc30 Reserved 762.
	volatile uint32_t RSVD_763;	 // 0xc34 Reserved 763.
	volatile uint32_t RSVD_764;	 // 0xc38 Reserved 764.
	volatile uint32_t RSVD_765;	 // 0xc3c Reserved 765.
	volatile uint32_t RSVD_766;	 // 0xc40 Reserved 766.
	volatile uint32_t RSVD_767;	 // 0xc44 Reserved 767.
	volatile uint32_t RSVD_768;	 // 0xc48 Reserved 768.
	volatile uint32_t RSVD_769;	 // 0xc4c Reserved 769.
	volatile uint32_t RSVD_770;	 // 0xc50 Reserved 770.
	volatile uint32_t RSVD_771;	 // 0xc54 Reserved 771.
	volatile uint32_t RSVD_772;	 // 0xc58 Reserved 772.
	volatile uint32_t RSVD_773;	 // 0xc5c Reserved 773.
	volatile uint32_t RSVD_774;	 // 0xc60 Reserved 774.
	volatile uint32_t RSVD_775;	 // 0xc64 Reserved 775.
	volatile uint32_t RSVD_776;	 // 0xc68 Reserved 776.
	volatile uint32_t RSVD_777;	 // 0xc6c Reserved 777.
	volatile uint32_t RSVD_778;	 // 0xc70 Reserved 778.
	volatile uint32_t RSVD_779;	 // 0xc74 Reserved 779.
	volatile uint32_t RSVD_780;	 // 0xc78 Reserved 780.
	volatile uint32_t RSVD_781;	 // 0xc7c Reserved 781.
	volatile uint32_t RSVD_782;	 // 0xc80 Reserved 782.
	volatile uint32_t RSVD_783;	 // 0xc84 Reserved 783.
	volatile uint32_t RSVD_784;	 // 0xc88 Reserved 784.
	volatile uint32_t RSVD_785;	 // 0xc8c Reserved 785.
	volatile uint32_t RSVD_786;	 // 0xc90 Reserved 786.
	volatile uint32_t RSVD_787;	 // 0xc94 Reserved 787.
	volatile uint32_t RSVD_788;	 // 0xc98 Reserved 788.
	volatile uint32_t RSVD_789;	 // 0xc9c Reserved 789.
	volatile uint32_t RSVD_790;	 // 0xca0 Reserved 790.
	volatile uint32_t RSVD_791;	 // 0xca4 Reserved 791.
	volatile uint32_t RSVD_792;	 // 0xca8 Reserved 792.
	volatile uint32_t RSVD_793;	 // 0xcac Reserved 793.
	volatile uint32_t RSVD_794;	 // 0xcb0 Reserved 794.
	volatile uint32_t RSVD_795;	 // 0xcb4 Reserved 795.
	volatile uint32_t RSVD_796;	 // 0xcb8 Reserved 796.
	volatile uint32_t RSVD_797;	 // 0xcbc Reserved 797.
	volatile uint32_t RSVD_798;	 // 0xcc0 Reserved 798.
	volatile uint32_t RSVD_799;	 // 0xcc4 Reserved 799.
	volatile uint32_t RSVD_800;	 // 0xcc8 Reserved 800.
	volatile uint32_t RSVD_801;	 // 0xccc Reserved 801.
	volatile uint32_t RSVD_802;	 // 0xcd0 Reserved 802.
	volatile uint32_t RSVD_803;	 // 0xcd4 Reserved 803.
	volatile uint32_t RSVD_804;	 // 0xcd8 Reserved 804.
	volatile uint32_t RSVD_805;	 // 0xcdc Reserved 805.
	volatile uint32_t RSVD_806;	 // 0xce0 Reserved 806.
	volatile uint32_t RSVD_807;	 // 0xce4 Reserved 807.
	volatile uint32_t RSVD_808;	 // 0xce8 Reserved 808.
	volatile uint32_t RSVD_809;	 // 0xcec Reserved 809.
	volatile uint32_t RSVD_810;	 // 0xcf0 Reserved 810.
	volatile uint32_t RSVD_811;	 // 0xcf4 Reserved 811.
	volatile uint32_t RSVD_812;	 // 0xcf8 Reserved 812.
	volatile uint32_t RSVD_813;	 // 0xcfc Reserved 813.
	volatile uint32_t RSVD_814;	 // 0xd00 Reserved 814.
	volatile uint32_t RSVD_815;	 // 0xd04 Reserved 815.
	volatile uint32_t RSVD_816;	 // 0xd08 Reserved 816.
	volatile uint32_t RSVD_817;	 // 0xd0c Reserved 817.
	volatile uint32_t RSVD_818;	 // 0xd10 Reserved 818.
	volatile uint32_t RSVD_819;	 // 0xd14 Reserved 819.
	volatile uint32_t RSVD_820;	 // 0xd18 Reserved 820.
	volatile uint32_t RSVD_821;	 // 0xd1c Reserved 821.
	volatile uint32_t RSVD_822;	 // 0xd20 Reserved 822.
	volatile uint32_t RSVD_823;	 // 0xd24 Reserved 823.
	volatile uint32_t RSVD_824;	 // 0xd28 Reserved 824.
	volatile uint32_t RSVD_825;	 // 0xd2c Reserved 825.
	volatile uint32_t RSVD_826;	 // 0xd30 Reserved 826.
	volatile uint32_t RSVD_827;	 // 0xd34 Reserved 827.
	volatile uint32_t RSVD_828;	 // 0xd38 Reserved 828.
	volatile uint32_t RSVD_829;	 // 0xd3c Reserved 829.
	volatile uint32_t RSVD_830;	 // 0xd40 Reserved 830.
	volatile uint32_t RSVD_831;	 // 0xd44 Reserved 831.
	volatile uint32_t RSVD_832;	 // 0xd48 Reserved 832.
	volatile uint32_t RSVD_833;	 // 0xd4c Reserved 833.
	volatile uint32_t RSVD_834;	 // 0xd50 Reserved 834.
	volatile uint32_t RSVD_835;	 // 0xd54 Reserved 835.
	volatile uint32_t RSVD_836;	 // 0xd58 Reserved 836.
	volatile uint32_t RSVD_837;	 // 0xd5c Reserved 837.
	volatile uint32_t RSVD_838;	 // 0xd60 Reserved 838.
	volatile uint32_t RSVD_839;	 // 0xd64 Reserved 839.
	volatile uint32_t RSVD_840;	 // 0xd68 Reserved 840.
	volatile uint32_t RSVD_841;	 // 0xd6c Reserved 841.
	volatile uint32_t RSVD_842;	 // 0xd70 Reserved 842.
	volatile uint32_t RSVD_843;	 // 0xd74 Reserved 843.
	volatile uint32_t RSVD_844;	 // 0xd78 Reserved 844.
	volatile uint32_t RSVD_845;	 // 0xd7c Reserved 845.
	volatile uint32_t RSVD_846;	 // 0xd80 Reserved 846.
	volatile uint32_t RSVD_847;	 // 0xd84 Reserved 847.
	volatile uint32_t RSVD_848;	 // 0xd88 Reserved 848.
	volatile uint32_t RSVD_849;	 // 0xd8c Reserved 849.
	volatile uint32_t RSVD_850;	 // 0xd90 Reserved 850.
	volatile uint32_t RSVD_851;	 // 0xd94 Reserved 851.
	volatile uint32_t RSVD_852;	 // 0xd98 Reserved 852.
	volatile uint32_t RSVD_853;	 // 0xd9c Reserved 853.
	volatile uint32_t RSVD_854;	 // 0xda0 Reserved 854.
	volatile uint32_t RSVD_855;	 // 0xda4 Reserved 855.
	volatile uint32_t RSVD_856;	 // 0xda8 Reserved 856.
	volatile uint32_t RSVD_857;	 // 0xdac Reserved 857.
	volatile uint32_t RSVD_858;	 // 0xdb0 Reserved 858.
	volatile uint32_t RSVD_859;	 // 0xdb4 Reserved 859.
	volatile uint32_t RSVD_860;	 // 0xdb8 Reserved 860.
	volatile uint32_t RSVD_861;	 // 0xdbc Reserved 861.
	volatile uint32_t RSVD_862;	 // 0xdc0 Reserved 862.
	volatile uint32_t RSVD_863;	 // 0xdc4 Reserved 863.
	volatile uint32_t RSVD_864;	 // 0xdc8 Reserved 864.
	volatile uint32_t RSVD_865;	 // 0xdcc Reserved 865.
	volatile uint32_t RSVD_866;	 // 0xdd0 Reserved 866.
	volatile uint32_t RSVD_867;	 // 0xdd4 Reserved 867.
	volatile uint32_t RSVD_868;	 // 0xdd8 Reserved 868.
	volatile uint32_t RSVD_869;	 // 0xddc Reserved 869.
	volatile uint32_t RSVD_870;	 // 0xde0 Reserved 870.
	volatile uint32_t RSVD_871;	 // 0xde4 Reserved 871.
	volatile uint32_t RSVD_872;	 // 0xde8 Reserved 872.
	volatile uint32_t RSVD_873;	 // 0xdec Reserved 873.
	volatile uint32_t RSVD_874;	 // 0xdf0 Reserved 874.
	volatile uint32_t RSVD_875;	 // 0xdf4 Reserved 875.
	volatile uint32_t RSVD_876;	 // 0xdf8 Reserved 876.
	volatile uint32_t RSVD_877;	 // 0xdfc Reserved 877.
	volatile uint32_t RSVD_878;	 // 0xe00 Reserved 878.
	volatile uint32_t RSVD_879;	 // 0xe04 Reserved 879.
	volatile uint32_t RSVD_880;	 // 0xe08 Reserved 880.
	volatile uint32_t RSVD_881;	 // 0xe0c Reserved 881.
	volatile uint32_t RSVD_882;	 // 0xe10 Reserved 882.
	volatile uint32_t RSVD_883;	 // 0xe14 Reserved 883.
	volatile uint32_t RSVD_884;	 // 0xe18 Reserved 884.
	volatile uint32_t RSVD_885;	 // 0xe1c Reserved 885.
	volatile uint32_t RSVD_886;	 // 0xe20 Reserved 886.
	volatile uint32_t RSVD_887;	 // 0xe24 Reserved 887.
	volatile uint32_t RSVD_888;	 // 0xe28 Reserved 888.
	volatile uint32_t RSVD_889;	 // 0xe2c Reserved 889.
	volatile uint32_t RSVD_890;	 // 0xe30 Reserved 890.
	volatile uint32_t RSVD_891;	 // 0xe34 Reserved 891.
	volatile uint32_t RSVD_892;	 // 0xe38 Reserved 892.
	volatile uint32_t RSVD_893;	 // 0xe3c Reserved 893.
	volatile uint32_t RSVD_894;	 // 0xe40 Reserved 894.
	volatile uint32_t RSVD_895;	 // 0xe44 Reserved 895.
	volatile uint32_t RSVD_896;	 // 0xe48 Reserved 896.
	volatile uint32_t RSVD_897;	 // 0xe4c Reserved 897.
	volatile uint32_t RSVD_898;	 // 0xe50 Reserved 898.
	volatile uint32_t RSVD_899;	 // 0xe54 Reserved 899.
	volatile uint32_t RSVD_900;	 // 0xe58 Reserved 900.
	volatile uint32_t RSVD_901;	 // 0xe5c Reserved 901.
	volatile uint32_t RSVD_902;	 // 0xe60 Reserved 902.
	volatile uint32_t RSVD_903;	 // 0xe64 Reserved 903.
	volatile uint32_t RSVD_904;	 // 0xe68 Reserved 904.
	volatile uint32_t RSVD_905;	 // 0xe6c Reserved 905.
	volatile uint32_t RSVD_906;	 // 0xe70 Reserved 906.
	volatile uint32_t RSVD_907;	 // 0xe74 Reserved 907.
	volatile uint32_t RSVD_908;	 // 0xe78 Reserved 908.
	volatile uint32_t RSVD_909;	 // 0xe7c Reserved 909.
	volatile uint32_t RSVD_910;	 // 0xe80 Reserved 910.
	volatile uint32_t RSVD_911;	 // 0xe84 Reserved 911.
	volatile uint32_t RSVD_912;	 // 0xe88 Reserved 912.
	volatile uint32_t RSVD_913;	 // 0xe8c Reserved 913.
	volatile uint32_t RSVD_914;	 // 0xe90 Reserved 914.
	volatile uint32_t RSVD_915;	 // 0xe94 Reserved 915.
	volatile uint32_t RSVD_916;	 // 0xe98 Reserved 916.
	volatile uint32_t RSVD_917;	 // 0xe9c Reserved 917.
	volatile uint32_t RSVD_918;	 // 0xea0 Reserved 918.
	volatile uint32_t RSVD_919;	 // 0xea4 Reserved 919.
	volatile uint32_t RSVD_920;	 // 0xea8 Reserved 920.
	volatile uint32_t RSVD_921;	 // 0xeac Reserved 921.
	volatile uint32_t RSVD_922;	 // 0xeb0 Reserved 922.
	volatile uint32_t RSVD_923;	 // 0xeb4 Reserved 923.
	volatile uint32_t RSVD_924;	 // 0xeb8 Reserved 924.
	volatile uint32_t RSVD_925;	 // 0xebc Reserved 925.
	volatile uint32_t RSVD_926;	 // 0xec0 Reserved 926.
	volatile uint32_t RSVD_927;	 // 0xec4 Reserved 927.
	volatile uint32_t RSVD_928;	 // 0xec8 Reserved 928.
	volatile uint32_t RSVD_929;	 // 0xecc Reserved 929.
	volatile uint32_t RSVD_930;	 // 0xed0 Reserved 930.
	volatile uint32_t RSVD_931;	 // 0xed4 Reserved 931.
	volatile uint32_t RSVD_932;	 // 0xed8 Reserved 932.
	volatile uint32_t RSVD_933;	 // 0xedc Reserved 933.
	volatile uint32_t RSVD_934;	 // 0xee0 Reserved 934.
	volatile uint32_t RSVD_935;	 // 0xee4 Reserved 935.
	volatile uint32_t RSVD_936;	 // 0xee8 Reserved 936.
	volatile uint32_t RSVD_937;	 // 0xeec Reserved 937.
	volatile uint32_t RSVD_938;	 // 0xef0 Reserved 938.
	volatile uint32_t RSVD_939;	 // 0xef4 Reserved 939.
	volatile uint32_t RSVD_940;	 // 0xef8 Reserved 940.
	volatile uint32_t RSVD_941;	 // 0xefc Reserved 941.
	volatile uint32_t RSVD_942;	 // 0xf00 Reserved 942.
	volatile uint32_t RSVD_943;	 // 0xf04 Reserved 943.
	volatile uint32_t RSVD_944;	 // 0xf08 Reserved 944.
	volatile uint32_t RSVD_945;	 // 0xf0c Reserved 945.
	volatile uint32_t RSVD_946;	 // 0xf10 Reserved 946.
	volatile uint32_t RSVD_947;	 // 0xf14 Reserved 947.
	volatile uint32_t RSVD_948;	 // 0xf18 Reserved 948.
	volatile uint32_t RSVD_949;	 // 0xf1c Reserved 949.
	volatile uint32_t RSVD_950;	 // 0xf20 Reserved 950.
	volatile uint32_t RSVD_951;	 // 0xf24 Reserved 951.
	volatile uint32_t RSVD_952;	 // 0xf28 Reserved 952.
	volatile uint32_t RSVD_953;	 // 0xf2c Reserved 953.
	volatile uint32_t RSVD_954;	 // 0xf30 Reserved 954.
	volatile uint32_t RSVD_955;	 // 0xf34 Reserved 955.
	volatile uint32_t RSVD_956;	 // 0xf38 Reserved 956.
	volatile uint32_t RSVD_957;	 // 0xf3c Reserved 957.
	volatile uint32_t RSVD_958;	 // 0xf40 Reserved 958.
	volatile uint32_t RSVD_959;	 // 0xf44 Reserved 959.
	volatile uint32_t RSVD_960;	 // 0xf48 Reserved 960.
	volatile uint32_t RSVD_961;	 // 0xf4c Reserved 961.
	volatile uint32_t RSVD_962;	 // 0xf50 Reserved 962.
	volatile uint32_t RSVD_963;	 // 0xf54 Reserved 963.
	volatile uint32_t RSVD_964;	 // 0xf58 Reserved 964.
	volatile uint32_t RSVD_965;	 // 0xf5c Reserved 965.
	volatile uint32_t RSVD_966;	 // 0xf60 Reserved 966.
	volatile uint32_t RSVD_967;	 // 0xf64 Reserved 967.
	volatile uint32_t RSVD_968;	 // 0xf68 Reserved 968.
	volatile uint32_t RSVD_969;	 // 0xf6c Reserved 969.
	volatile uint32_t RSVD_970;	 // 0xf70 Reserved 970.
	volatile uint32_t RSVD_971;	 // 0xf74 Reserved 971.
	volatile uint32_t RSVD_972;	 // 0xf78 Reserved 972.
	volatile uint32_t RSVD_973;	 // 0xf7c Reserved 973.
	volatile uint32_t RSVD_974;	 // 0xf80 Reserved 974.
	volatile uint32_t RSVD_975;	 // 0xf84 Reserved 975.
	volatile uint32_t RSVD_976;	 // 0xf88 Reserved 976.
	volatile uint32_t RSVD_977;	 // 0xf8c Reserved 977.
	volatile uint32_t RSVD_978;	 // 0xf90 Reserved 978.
	volatile uint32_t RSVD_979;	 // 0xf94 Reserved 979.
	volatile uint32_t RSVD_980;	 // 0xf98 Reserved 980.
	volatile uint32_t RSVD_981;	 // 0xf9c Reserved 981.
	volatile uint32_t RSVD_982;	 // 0xfa0 Reserved 982.
	volatile uint32_t RSVD_983;	 // 0xfa4 Reserved 983.
	volatile uint32_t RSVD_984;	 // 0xfa8 Reserved 984.
	volatile uint32_t RSVD_985;	 // 0xfac Reserved 985.
	volatile uint32_t RSVD_986;	 // 0xfb0 Reserved 986.
	volatile uint32_t RSVD_987;	 // 0xfb4 Reserved 987.
	volatile uint32_t RSVD_988;	 // 0xfb8 Reserved 988.
	volatile uint32_t RSVD_989;	 // 0xfbc Reserved 989.
	volatile uint32_t RSVD_990;	 // 0xfc0 Reserved 990.
	volatile uint32_t RSVD_991;	 // 0xfc4 Reserved 991.
	volatile uint32_t RSVD_992;	 // 0xfc8 Reserved 992.
	volatile uint32_t RSVD_993;	 // 0xfcc Reserved 993.
	volatile uint32_t RSVD_994;	 // 0xfd0 Reserved 994.
	volatile uint32_t RSVD_995;	 // 0xfd4 Reserved 995.
	volatile uint32_t RSVD_996;	 // 0xfd8 Reserved 996.
	volatile uint32_t RSVD_997;	 // 0xfdc Reserved 997.
	volatile uint32_t RSVD_998;	 // 0xfe0 Reserved 998.
	volatile uint32_t RSVD_999;	 // 0xfe4 Reserved 999.
	volatile uint32_t RSVD_1000;	 // 0xfe8 Reserved 1000.
	volatile uint32_t RSVD_1001;	 // 0xfec Reserved 1001.
	volatile uint32_t RSVD_1002;	 // 0xff0 Reserved 1002.
	volatile uint32_t RSVD_1003;	 // 0xff4 Reserved 1003.
	volatile uint32_t RSVD_1004;	 // 0xff8 Reserved 1004.
	volatile uint32_t RSVD_1005;	 // 0xffc Reserved 1005.
	volatile uint32_t RSVD_1006;	 // 0x1000 Reserved 1006.
	volatile uint32_t RSVD_1007;	 // 0x1004 Reserved 1007.
	volatile uint32_t RSVD_1008;	 // 0x1008 Reserved 1008.
	volatile uint32_t RSVD_1009;	 // 0x100c Reserved 1009.
	volatile uint32_t RSVD_1010;	 // 0x1010 Reserved 1010.
	volatile uint32_t RSVD_1011;	 // 0x1014 Reserved 1011.
	volatile uint32_t RSVD_1012;	 // 0x1018 Reserved 1012.
	volatile uint32_t RSVD_1013;	 // 0x101c Reserved 1013.
	volatile uint32_t RSVD_1014;	 // 0x1020 Reserved 1014.
	volatile uint32_t RSVD_1015;	 // 0x1024 Reserved 1015.
	volatile uint32_t RSVD_1016;	 // 0x1028 Reserved 1016.
	volatile uint32_t RSVD_1017;	 // 0x102c Reserved 1017.
	volatile uint32_t RSVD_1018;	 // 0x1030 Reserved 1018.
	volatile uint32_t RSVD_1019;	 // 0x1034 Reserved 1019.
	volatile uint32_t RSVD_1020;	 // 0x1038 Reserved 1020.
	volatile uint32_t RSVD_1021;	 // 0x103c Reserved 1021.
	volatile uint32_t RSVD_1022;	 // 0x1040 Reserved 1022.
	volatile uint32_t RSVD_1023;	 // 0x1044 Reserved 1023.
	volatile uint32_t RSVD_1024;	 // 0x1048 Reserved 1024.
	volatile uint32_t RSVD_1025;	 // 0x104c Reserved 1025.
	volatile uint32_t RSVD_1026;	 // 0x1050 Reserved 1026.
	volatile uint32_t RSVD_1027;	 // 0x1054 Reserved 1027.
	volatile uint32_t RSVD_1028;	 // 0x1058 Reserved 1028.
	volatile uint32_t RSVD_1029;	 // 0x105c Reserved 1029.
	volatile uint32_t RSVD_1030;	 // 0x1060 Reserved 1030.
	volatile uint32_t RSVD_1031;	 // 0x1064 Reserved 1031.
	volatile uint32_t RSVD_1032;	 // 0x1068 Reserved 1032.
	volatile uint32_t RSVD_1033;	 // 0x106c Reserved 1033.
	volatile uint32_t RSVD_1034;	 // 0x1070 Reserved 1034.
	volatile uint32_t RSVD_1035;	 // 0x1074 Reserved 1035.
	volatile uint32_t RSVD_1036;	 // 0x1078 Reserved 1036.
	volatile uint32_t RSVD_1037;	 // 0x107c Reserved 1037.
	volatile uint32_t RSVD_1038;	 // 0x1080 Reserved 1038.
	volatile uint32_t RSVD_1039;	 // 0x1084 Reserved 1039.
	volatile uint32_t RSVD_1040;	 // 0x1088 Reserved 1040.
	volatile uint32_t RSVD_1041;	 // 0x108c Reserved 1041.
	volatile uint32_t RSVD_1042;	 // 0x1090 Reserved 1042.
	volatile uint32_t RSVD_1043;	 // 0x1094 Reserved 1043.
	volatile uint32_t RSVD_1044;	 // 0x1098 Reserved 1044.
	volatile uint32_t RSVD_1045;	 // 0x109c Reserved 1045.
	volatile uint32_t RSVD_1046;	 // 0x10a0 Reserved 1046.
	volatile uint32_t RSVD_1047;	 // 0x10a4 Reserved 1047.
	volatile uint32_t RSVD_1048;	 // 0x10a8 Reserved 1048.
	volatile uint32_t RSVD_1049;	 // 0x10ac Reserved 1049.
	volatile uint32_t RSVD_1050;	 // 0x10b0 Reserved 1050.
	volatile uint32_t RSVD_1051;	 // 0x10b4 Reserved 1051.
	volatile uint32_t RSVD_1052;	 // 0x10b8 Reserved 1052.
	volatile uint32_t RSVD_1053;	 // 0x10bc Reserved 1053.
	volatile uint32_t RSVD_1054;	 // 0x10c0 Reserved 1054.
	volatile uint32_t RSVD_1055;	 // 0x10c4 Reserved 1055.
	volatile uint32_t RSVD_1056;	 // 0x10c8 Reserved 1056.
	volatile uint32_t RSVD_1057;	 // 0x10cc Reserved 1057.
	volatile uint32_t RSVD_1058;	 // 0x10d0 Reserved 1058.
	volatile uint32_t RSVD_1059;	 // 0x10d4 Reserved 1059.
	volatile uint32_t RSVD_1060;	 // 0x10d8 Reserved 1060.
	volatile uint32_t RSVD_1061;	 // 0x10dc Reserved 1061.
	volatile uint32_t RSVD_1062;	 // 0x10e0 Reserved 1062.
	volatile uint32_t RSVD_1063;	 // 0x10e4 Reserved 1063.
	volatile uint32_t RSVD_1064;	 // 0x10e8 Reserved 1064.
	volatile uint32_t RSVD_1065;	 // 0x10ec Reserved 1065.
	volatile uint32_t RSVD_1066;	 // 0x10f0 Reserved 1066.
	volatile uint32_t RSVD_1067;	 // 0x10f4 Reserved 1067.
	volatile uint32_t RSVD_1068;	 // 0x10f8 Reserved 1068.
	volatile uint32_t RSVD_1069;	 // 0x10fc Reserved 1069.
	volatile uint32_t RSVD_1070;	 // 0x1100 Reserved 1070.
	volatile uint32_t RSVD_1071;	 // 0x1104 Reserved 1071.
	volatile uint32_t RSVD_1072;	 // 0x1108 Reserved 1072.
	volatile uint32_t RSVD_1073;	 // 0x110c Reserved 1073.
	volatile uint32_t RSVD_1074;	 // 0x1110 Reserved 1074.
	volatile uint32_t RSVD_1075;	 // 0x1114 Reserved 1075.
	volatile uint32_t RSVD_1076;	 // 0x1118 Reserved 1076.
	volatile uint32_t RSVD_1077;	 // 0x111c Reserved 1077.
	volatile uint32_t RSVD_1078;	 // 0x1120 Reserved 1078.
	volatile uint32_t RSVD_1079;	 // 0x1124 Reserved 1079.
	volatile uint32_t RSVD_1080;	 // 0x1128 Reserved 1080.
	volatile uint32_t RSVD_1081;	 // 0x112c Reserved 1081.
	volatile uint32_t RSVD_1082;	 // 0x1130 Reserved 1082.
	volatile uint32_t RSVD_1083;	 // 0x1134 Reserved 1083.
	volatile uint32_t RSVD_1084;	 // 0x1138 Reserved 1084.
	volatile uint32_t RSVD_1085;	 // 0x113c Reserved 1085.
	volatile uint32_t RSVD_1086;	 // 0x1140 Reserved 1086.
	volatile uint32_t RSVD_1087;	 // 0x1144 Reserved 1087.
	volatile uint32_t RSVD_1088;	 // 0x1148 Reserved 1088.
	volatile uint32_t RSVD_1089;	 // 0x114c Reserved 1089.
	volatile uint32_t RSVD_1090;	 // 0x1150 Reserved 1090.
	volatile uint32_t RSVD_1091;	 // 0x1154 Reserved 1091.
	volatile uint32_t RSVD_1092;	 // 0x1158 Reserved 1092.
	volatile uint32_t RSVD_1093;	 // 0x115c Reserved 1093.
	volatile uint32_t RSVD_1094;	 // 0x1160 Reserved 1094.
	volatile uint32_t RSVD_1095;	 // 0x1164 Reserved 1095.
	volatile uint32_t RSVD_1096;	 // 0x1168 Reserved 1096.
	volatile uint32_t RSVD_1097;	 // 0x116c Reserved 1097.
	volatile uint32_t RSVD_1098;	 // 0x1170 Reserved 1098.
	volatile uint32_t RSVD_1099;	 // 0x1174 Reserved 1099.
	volatile uint32_t RSVD_1100;	 // 0x1178 Reserved 1100.
	volatile uint32_t RSVD_1101;	 // 0x117c Reserved 1101.
	volatile uint32_t RSVD_1102;	 // 0x1180 Reserved 1102.
	volatile uint32_t RSVD_1103;	 // 0x1184 Reserved 1103.
	volatile uint32_t RSVD_1104;	 // 0x1188 Reserved 1104.
	volatile uint32_t RSVD_1105;	 // 0x118c Reserved 1105.
	volatile uint32_t RSVD_1106;	 // 0x1190 Reserved 1106.
	volatile uint32_t RSVD_1107;	 // 0x1194 Reserved 1107.
	volatile uint32_t RSVD_1108;	 // 0x1198 Reserved 1108.
	volatile uint32_t RSVD_1109;	 // 0x119c Reserved 1109.
	volatile uint32_t RSVD_1110;	 // 0x11a0 Reserved 1110.
	volatile uint32_t RSVD_1111;	 // 0x11a4 Reserved 1111.
	volatile uint32_t RSVD_1112;	 // 0x11a8 Reserved 1112.
	volatile uint32_t RSVD_1113;	 // 0x11ac Reserved 1113.
	volatile uint32_t RSVD_1114;	 // 0x11b0 Reserved 1114.
	volatile uint32_t RSVD_1115;	 // 0x11b4 Reserved 1115.
	volatile uint32_t RSVD_1116;	 // 0x11b8 Reserved 1116.
	volatile uint32_t RSVD_1117;	 // 0x11bc Reserved 1117.
	volatile uint32_t RSVD_1118;	 // 0x11c0 Reserved 1118.
	volatile uint32_t RSVD_1119;	 // 0x11c4 Reserved 1119.
	volatile uint32_t RSVD_1120;	 // 0x11c8 Reserved 1120.
	volatile uint32_t RSVD_1121;	 // 0x11cc Reserved 1121.
	volatile uint32_t RSVD_1122;	 // 0x11d0 Reserved 1122.
	volatile uint32_t RSVD_1123;	 // 0x11d4 Reserved 1123.
	volatile uint32_t RSVD_1124;	 // 0x11d8 Reserved 1124.
	volatile uint32_t RSVD_1125;	 // 0x11dc Reserved 1125.
	volatile uint32_t RSVD_1126;	 // 0x11e0 Reserved 1126.
	volatile uint32_t RSVD_1127;	 // 0x11e4 Reserved 1127.
	volatile uint32_t RSVD_1128;	 // 0x11e8 Reserved 1128.
	volatile uint32_t RSVD_1129;	 // 0x11ec Reserved 1129.
	volatile uint32_t RSVD_1130;	 // 0x11f0 Reserved 1130.
	volatile uint32_t RSVD_1131;	 // 0x11f4 Reserved 1131.
	volatile uint32_t RSVD_1132;	 // 0x11f8 Reserved 1132.
	volatile uint32_t RSVD_1133;	 // 0x11fc Reserved 1133.
	volatile uint32_t RSVD_1134;	 // 0x1200 Reserved 1134.
	volatile uint32_t RSVD_1135;	 // 0x1204 Reserved 1135.
	volatile uint32_t RSVD_1136;	 // 0x1208 Reserved 1136.
	volatile uint32_t RSVD_1137;	 // 0x120c Reserved 1137.
	volatile uint32_t RSVD_1138;	 // 0x1210 Reserved 1138.
	volatile uint32_t RSVD_1139;	 // 0x1214 Reserved 1139.
	volatile uint32_t RSVD_1140;	 // 0x1218 Reserved 1140.
	volatile uint32_t RSVD_1141;	 // 0x121c Reserved 1141.
	volatile uint32_t RSVD_1142;	 // 0x1220 Reserved 1142.
	volatile uint32_t RSVD_1143;	 // 0x1224 Reserved 1143.
	volatile uint32_t RSVD_1144;	 // 0x1228 Reserved 1144.
	volatile uint32_t RSVD_1145;	 // 0x122c Reserved 1145.
	volatile uint32_t RSVD_1146;	 // 0x1230 Reserved 1146.
	volatile uint32_t RSVD_1147;	 // 0x1234 Reserved 1147.
	volatile uint32_t RSVD_1148;	 // 0x1238 Reserved 1148.
	volatile uint32_t RSVD_1149;	 // 0x123c Reserved 1149.
	volatile uint32_t RSVD_1150;	 // 0x1240 Reserved 1150.
	volatile uint32_t RSVD_1151;	 // 0x1244 Reserved 1151.
	volatile uint32_t RSVD_1152;	 // 0x1248 Reserved 1152.
	volatile uint32_t RSVD_1153;	 // 0x124c Reserved 1153.
	volatile uint32_t RSVD_1154;	 // 0x1250 Reserved 1154.
	volatile uint32_t RSVD_1155;	 // 0x1254 Reserved 1155.
	volatile uint32_t RSVD_1156;	 // 0x1258 Reserved 1156.
	volatile uint32_t RSVD_1157;	 // 0x125c Reserved 1157.
	volatile uint32_t RSVD_1158;	 // 0x1260 Reserved 1158.
	volatile uint32_t RSVD_1159;	 // 0x1264 Reserved 1159.
	volatile uint32_t RSVD_1160;	 // 0x1268 Reserved 1160.
	volatile uint32_t RSVD_1161;	 // 0x126c Reserved 1161.
	volatile uint32_t RSVD_1162;	 // 0x1270 Reserved 1162.
	volatile uint32_t RSVD_1163;	 // 0x1274 Reserved 1163.
	volatile uint32_t RSVD_1164;	 // 0x1278 Reserved 1164.
	volatile uint32_t RSVD_1165;	 // 0x127c Reserved 1165.
	volatile uint32_t RSVD_1166;	 // 0x1280 Reserved 1166.
	volatile uint32_t RSVD_1167;	 // 0x1284 Reserved 1167.
	volatile uint32_t RSVD_1168;	 // 0x1288 Reserved 1168.
	volatile uint32_t RSVD_1169;	 // 0x128c Reserved 1169.
	volatile uint32_t RSVD_1170;	 // 0x1290 Reserved 1170.
	volatile uint32_t RSVD_1171;	 // 0x1294 Reserved 1171.
	volatile uint32_t RSVD_1172;	 // 0x1298 Reserved 1172.
	volatile uint32_t RSVD_1173;	 // 0x129c Reserved 1173.
	volatile uint32_t RSVD_1174;	 // 0x12a0 Reserved 1174.
	volatile uint32_t RSVD_1175;	 // 0x12a4 Reserved 1175.
	volatile uint32_t RSVD_1176;	 // 0x12a8 Reserved 1176.
	volatile uint32_t RSVD_1177;	 // 0x12ac Reserved 1177.
	volatile uint32_t RSVD_1178;	 // 0x12b0 Reserved 1178.
	volatile uint32_t RSVD_1179;	 // 0x12b4 Reserved 1179.
	volatile uint32_t RSVD_1180;	 // 0x12b8 Reserved 1180.
	volatile uint32_t RSVD_1181;	 // 0x12bc Reserved 1181.
	volatile uint32_t RSVD_1182;	 // 0x12c0 Reserved 1182.
	volatile uint32_t RSVD_1183;	 // 0x12c4 Reserved 1183.
	volatile uint32_t RSVD_1184;	 // 0x12c8 Reserved 1184.
	volatile uint32_t RSVD_1185;	 // 0x12cc Reserved 1185.
	volatile uint32_t RSVD_1186;	 // 0x12d0 Reserved 1186.
	volatile uint32_t RSVD_1187;	 // 0x12d4 Reserved 1187.
	volatile uint32_t RSVD_1188;	 // 0x12d8 Reserved 1188.
	volatile uint32_t RSVD_1189;	 // 0x12dc Reserved 1189.
	volatile uint32_t RSVD_1190;	 // 0x12e0 Reserved 1190.
	volatile uint32_t RSVD_1191;	 // 0x12e4 Reserved 1191.
	volatile uint32_t RSVD_1192;	 // 0x12e8 Reserved 1192.
	volatile uint32_t RSVD_1193;	 // 0x12ec Reserved 1193.
	volatile uint32_t RSVD_1194;	 // 0x12f0 Reserved 1194.
	volatile uint32_t RSVD_1195;	 // 0x12f4 Reserved 1195.
	volatile uint32_t RSVD_1196;	 // 0x12f8 Reserved 1196.
	volatile uint32_t RSVD_1197;	 // 0x12fc Reserved 1197.
	volatile uint32_t RSVD_1198;	 // 0x1300 Reserved 1198.
	volatile uint32_t RSVD_1199;	 // 0x1304 Reserved 1199.
	volatile uint32_t RSVD_1200;	 // 0x1308 Reserved 1200.
	volatile uint32_t RSVD_1201;	 // 0x130c Reserved 1201.
	volatile uint32_t RSVD_1202;	 // 0x1310 Reserved 1202.
	volatile uint32_t RSVD_1203;	 // 0x1314 Reserved 1203.
	volatile uint32_t RSVD_1204;	 // 0x1318 Reserved 1204.
	volatile uint32_t RSVD_1205;	 // 0x131c Reserved 1205.
	volatile uint32_t RSVD_1206;	 // 0x1320 Reserved 1206.
	volatile uint32_t RSVD_1207;	 // 0x1324 Reserved 1207.
	volatile uint32_t RSVD_1208;	 // 0x1328 Reserved 1208.
	volatile uint32_t RSVD_1209;	 // 0x132c Reserved 1209.
	volatile uint32_t RSVD_1210;	 // 0x1330 Reserved 1210.
	volatile uint32_t RSVD_1211;	 // 0x1334 Reserved 1211.
	volatile uint32_t RSVD_1212;	 // 0x1338 Reserved 1212.
	volatile uint32_t RSVD_1213;	 // 0x133c Reserved 1213.
	volatile uint32_t RSVD_1214;	 // 0x1340 Reserved 1214.
	volatile uint32_t RSVD_1215;	 // 0x1344 Reserved 1215.
	volatile uint32_t RSVD_1216;	 // 0x1348 Reserved 1216.
	volatile uint32_t RSVD_1217;	 // 0x134c Reserved 1217.
	volatile uint32_t RSVD_1218;	 // 0x1350 Reserved 1218.
	volatile uint32_t RSVD_1219;	 // 0x1354 Reserved 1219.
	volatile uint32_t RSVD_1220;	 // 0x1358 Reserved 1220.
	volatile uint32_t RSVD_1221;	 // 0x135c Reserved 1221.
	volatile uint32_t RSVD_1222;	 // 0x1360 Reserved 1222.
	volatile uint32_t RSVD_1223;	 // 0x1364 Reserved 1223.
	volatile uint32_t RSVD_1224;	 // 0x1368 Reserved 1224.
	volatile uint32_t RSVD_1225;	 // 0x136c Reserved 1225.
	volatile uint32_t RSVD_1226;	 // 0x1370 Reserved 1226.
	volatile uint32_t RSVD_1227;	 // 0x1374 Reserved 1227.
	volatile uint32_t RSVD_1228;	 // 0x1378 Reserved 1228.
	volatile uint32_t RSVD_1229;	 // 0x137c Reserved 1229.
	volatile uint32_t RSVD_1230;	 // 0x1380 Reserved 1230.
	volatile uint32_t RSVD_1231;	 // 0x1384 Reserved 1231.
	volatile uint32_t RSVD_1232;	 // 0x1388 Reserved 1232.
	volatile uint32_t RSVD_1233;	 // 0x138c Reserved 1233.
	volatile uint32_t RSVD_1234;	 // 0x1390 Reserved 1234.
	volatile uint32_t RSVD_1235;	 // 0x1394 Reserved 1235.
	volatile uint32_t RSVD_1236;	 // 0x1398 Reserved 1236.
	volatile uint32_t RSVD_1237;	 // 0x139c Reserved 1237.
	volatile uint32_t RSVD_1238;	 // 0x13a0 Reserved 1238.
	volatile uint32_t RSVD_1239;	 // 0x13a4 Reserved 1239.
	volatile uint32_t RSVD_1240;	 // 0x13a8 Reserved 1240.
	volatile uint32_t RSVD_1241;	 // 0x13ac Reserved 1241.
	volatile uint32_t RSVD_1242;	 // 0x13b0 Reserved 1242.
	volatile uint32_t RSVD_1243;	 // 0x13b4 Reserved 1243.
	volatile uint32_t RSVD_1244;	 // 0x13b8 Reserved 1244.
	volatile uint32_t RSVD_1245;	 // 0x13bc Reserved 1245.
	volatile uint32_t RSVD_1246;	 // 0x13c0 Reserved 1246.
	volatile uint32_t RSVD_1247;	 // 0x13c4 Reserved 1247.
	volatile uint32_t RSVD_1248;	 // 0x13c8 Reserved 1248.
	volatile uint32_t RSVD_1249;	 // 0x13cc Reserved 1249.
	volatile uint32_t RSVD_1250;	 // 0x13d0 Reserved 1250.
	volatile uint32_t RSVD_1251;	 // 0x13d4 Reserved 1251.
	volatile uint32_t RSVD_1252;	 // 0x13d8 Reserved 1252.
	volatile uint32_t RSVD_1253;	 // 0x13dc Reserved 1253.
	volatile uint32_t RSVD_1254;	 // 0x13e0 Reserved 1254.
	volatile uint32_t RSVD_1255;	 // 0x13e4 Reserved 1255.
	volatile uint32_t RSVD_1256;	 // 0x13e8 Reserved 1256.
	volatile uint32_t RSVD_1257;	 // 0x13ec Reserved 1257.
	volatile uint32_t RSVD_1258;	 // 0x13f0 Reserved 1258.
	volatile uint32_t RSVD_1259;	 // 0x13f4 Reserved 1259.
	volatile uint32_t RSVD_1260;	 // 0x13f8 Reserved 1260.
	volatile uint32_t RSVD_1261;	 // 0x13fc Reserved 1261.
	volatile uint32_t RSVD_1262;	 // 0x1400 Reserved 1262.
	volatile uint32_t RSVD_1263;	 // 0x1404 Reserved 1263.
	volatile uint32_t RSVD_1264;	 // 0x1408 Reserved 1264.
	volatile uint32_t RSVD_1265;	 // 0x140c Reserved 1265.
	volatile uint32_t RSVD_1266;	 // 0x1410 Reserved 1266.
	volatile uint32_t RSVD_1267;	 // 0x1414 Reserved 1267.
	volatile uint32_t RSVD_1268;	 // 0x1418 Reserved 1268.
	volatile uint32_t RSVD_1269;	 // 0x141c Reserved 1269.
	volatile uint32_t RSVD_1270;	 // 0x1420 Reserved 1270.
	volatile uint32_t RSVD_1271;	 // 0x1424 Reserved 1271.
	volatile uint32_t RSVD_1272;	 // 0x1428 Reserved 1272.
	volatile uint32_t RSVD_1273;	 // 0x142c Reserved 1273.
	volatile uint32_t RSVD_1274;	 // 0x1430 Reserved 1274.
	volatile uint32_t RSVD_1275;	 // 0x1434 Reserved 1275.
	volatile uint32_t RSVD_1276;	 // 0x1438 Reserved 1276.
	volatile uint32_t RSVD_1277;	 // 0x143c Reserved 1277.
	volatile uint32_t RSVD_1278;	 // 0x1440 Reserved 1278.
	volatile uint32_t RSVD_1279;	 // 0x1444 Reserved 1279.
	volatile uint32_t RSVD_1280;	 // 0x1448 Reserved 1280.
	volatile uint32_t RSVD_1281;	 // 0x144c Reserved 1281.
	volatile uint32_t RSVD_1282;	 // 0x1450 Reserved 1282.
	volatile uint32_t RSVD_1283;	 // 0x1454 Reserved 1283.
	volatile uint32_t RSVD_1284;	 // 0x1458 Reserved 1284.
	volatile uint32_t RSVD_1285;	 // 0x145c Reserved 1285.
	volatile uint32_t RSVD_1286;	 // 0x1460 Reserved 1286.
	volatile uint32_t RSVD_1287;	 // 0x1464 Reserved 1287.
	volatile uint32_t RSVD_1288;	 // 0x1468 Reserved 1288.
	volatile uint32_t RSVD_1289;	 // 0x146c Reserved 1289.
	volatile uint32_t RSVD_1290;	 // 0x1470 Reserved 1290.
	volatile uint32_t RSVD_1291;	 // 0x1474 Reserved 1291.
	volatile uint32_t RSVD_1292;	 // 0x1478 Reserved 1292.
	volatile uint32_t RSVD_1293;	 // 0x147c Reserved 1293.
	volatile uint32_t RSVD_1294;	 // 0x1480 Reserved 1294.
	volatile uint32_t RSVD_1295;	 // 0x1484 Reserved 1295.
	volatile uint32_t RSVD_1296;	 // 0x1488 Reserved 1296.
	volatile uint32_t RSVD_1297;	 // 0x148c Reserved 1297.
	volatile uint32_t RSVD_1298;	 // 0x1490 Reserved 1298.
	volatile uint32_t RSVD_1299;	 // 0x1494 Reserved 1299.
	volatile uint32_t RSVD_1300;	 // 0x1498 Reserved 1300.
	volatile uint32_t RSVD_1301;	 // 0x149c Reserved 1301.
	volatile uint32_t RSVD_1302;	 // 0x14a0 Reserved 1302.
	volatile uint32_t RSVD_1303;	 // 0x14a4 Reserved 1303.
	volatile uint32_t RSVD_1304;	 // 0x14a8 Reserved 1304.
	volatile uint32_t RSVD_1305;	 // 0x14ac Reserved 1305.
	volatile uint32_t RSVD_1306;	 // 0x14b0 Reserved 1306.
	volatile uint32_t RSVD_1307;	 // 0x14b4 Reserved 1307.
	volatile uint32_t RSVD_1308;	 // 0x14b8 Reserved 1308.
	volatile uint32_t RSVD_1309;	 // 0x14bc Reserved 1309.
	volatile uint32_t RSVD_1310;	 // 0x14c0 Reserved 1310.
	volatile uint32_t RSVD_1311;	 // 0x14c4 Reserved 1311.
	volatile uint32_t RSVD_1312;	 // 0x14c8 Reserved 1312.
	volatile uint32_t RSVD_1313;	 // 0x14cc Reserved 1313.
	volatile uint32_t RSVD_1314;	 // 0x14d0 Reserved 1314.
	volatile uint32_t RSVD_1315;	 // 0x14d4 Reserved 1315.
	volatile uint32_t RSVD_1316;	 // 0x14d8 Reserved 1316.
	volatile uint32_t RSVD_1317;	 // 0x14dc Reserved 1317.
	volatile uint32_t RSVD_1318;	 // 0x14e0 Reserved 1318.
	volatile uint32_t RSVD_1319;	 // 0x14e4 Reserved 1319.
	volatile uint32_t RSVD_1320;	 // 0x14e8 Reserved 1320.
	volatile uint32_t RSVD_1321;	 // 0x14ec Reserved 1321.
	volatile uint32_t RSVD_1322;	 // 0x14f0 Reserved 1322.
	volatile uint32_t RSVD_1323;	 // 0x14f4 Reserved 1323.
	volatile uint32_t RSVD_1324;	 // 0x14f8 Reserved 1324.
	volatile uint32_t RSVD_1325;	 // 0x14fc Reserved 1325.
	volatile uint32_t RSVD_1326;	 // 0x1500 Reserved 1326.
	volatile uint32_t RSVD_1327;	 // 0x1504 Reserved 1327.
	volatile uint32_t RSVD_1328;	 // 0x1508 Reserved 1328.
	volatile uint32_t RSVD_1329;	 // 0x150c Reserved 1329.
	volatile uint32_t RSVD_1330;	 // 0x1510 Reserved 1330.
	volatile uint32_t RSVD_1331;	 // 0x1514 Reserved 1331.
	volatile uint32_t RSVD_1332;	 // 0x1518 Reserved 1332.
	volatile uint32_t RSVD_1333;	 // 0x151c Reserved 1333.
	volatile uint32_t RSVD_1334;	 // 0x1520 Reserved 1334.
	volatile uint32_t RSVD_1335;	 // 0x1524 Reserved 1335.
	volatile uint32_t RSVD_1336;	 // 0x1528 Reserved 1336.
	volatile uint32_t RSVD_1337;	 // 0x152c Reserved 1337.
	volatile uint32_t RSVD_1338;	 // 0x1530 Reserved 1338.
	volatile uint32_t RSVD_1339;	 // 0x1534 Reserved 1339.
	volatile uint32_t RSVD_1340;	 // 0x1538 Reserved 1340.
	volatile uint32_t RSVD_1341;	 // 0x153c Reserved 1341.
	volatile uint32_t RSVD_1342;	 // 0x1540 Reserved 1342.
	volatile uint32_t RSVD_1343;	 // 0x1544 Reserved 1343.
	volatile uint32_t RSVD_1344;	 // 0x1548 Reserved 1344.
	volatile uint32_t RSVD_1345;	 // 0x154c Reserved 1345.
	volatile uint32_t RSVD_1346;	 // 0x1550 Reserved 1346.
	volatile uint32_t RSVD_1347;	 // 0x1554 Reserved 1347.
	volatile uint32_t RSVD_1348;	 // 0x1558 Reserved 1348.
	volatile uint32_t RSVD_1349;	 // 0x155c Reserved 1349.
	volatile uint32_t RSVD_1350;	 // 0x1560 Reserved 1350.
	volatile uint32_t RSVD_1351;	 // 0x1564 Reserved 1351.
	volatile uint32_t RSVD_1352;	 // 0x1568 Reserved 1352.
	volatile uint32_t RSVD_1353;	 // 0x156c Reserved 1353.
	volatile uint32_t RSVD_1354;	 // 0x1570 Reserved 1354.
	volatile uint32_t RSVD_1355;	 // 0x1574 Reserved 1355.
	volatile uint32_t RSVD_1356;	 // 0x1578 Reserved 1356.
	volatile uint32_t RSVD_1357;	 // 0x157c Reserved 1357.
	volatile uint32_t RSVD_1358;	 // 0x1580 Reserved 1358.
	volatile uint32_t RSVD_1359;	 // 0x1584 Reserved 1359.
	volatile uint32_t RSVD_1360;	 // 0x1588 Reserved 1360.
	volatile uint32_t RSVD_1361;	 // 0x158c Reserved 1361.
	volatile uint32_t RSVD_1362;	 // 0x1590 Reserved 1362.
	volatile uint32_t RSVD_1363;	 // 0x1594 Reserved 1363.
	volatile uint32_t RSVD_1364;	 // 0x1598 Reserved 1364.
	volatile uint32_t RSVD_1365;	 // 0x159c Reserved 1365.
	volatile uint32_t RSVD_1366;	 // 0x15a0 Reserved 1366.
	volatile uint32_t RSVD_1367;	 // 0x15a4 Reserved 1367.
	volatile uint32_t RSVD_1368;	 // 0x15a8 Reserved 1368.
	volatile uint32_t RSVD_1369;	 // 0x15ac Reserved 1369.
	volatile uint32_t RSVD_1370;	 // 0x15b0 Reserved 1370.
	volatile uint32_t RSVD_1371;	 // 0x15b4 Reserved 1371.
	volatile uint32_t RSVD_1372;	 // 0x15b8 Reserved 1372.
	volatile uint32_t RSVD_1373;	 // 0x15bc Reserved 1373.
	volatile uint32_t RSVD_1374;	 // 0x15c0 Reserved 1374.
	volatile uint32_t RSVD_1375;	 // 0x15c4 Reserved 1375.
	volatile uint32_t RSVD_1376;	 // 0x15c8 Reserved 1376.
	volatile uint32_t RSVD_1377;	 // 0x15cc Reserved 1377.
	volatile uint32_t RSVD_1378;	 // 0x15d0 Reserved 1378.
	volatile uint32_t RSVD_1379;	 // 0x15d4 Reserved 1379.
	volatile uint32_t RSVD_1380;	 // 0x15d8 Reserved 1380.
	volatile uint32_t RSVD_1381;	 // 0x15dc Reserved 1381.
	volatile uint32_t RSVD_1382;	 // 0x15e0 Reserved 1382.
	volatile uint32_t RSVD_1383;	 // 0x15e4 Reserved 1383.
	volatile uint32_t RSVD_1384;	 // 0x15e8 Reserved 1384.
	volatile uint32_t RSVD_1385;	 // 0x15ec Reserved 1385.
	volatile uint32_t RSVD_1386;	 // 0x15f0 Reserved 1386.
	volatile uint32_t RSVD_1387;	 // 0x15f4 Reserved 1387.
	volatile uint32_t RSVD_1388;	 // 0x15f8 Reserved 1388.
	volatile uint32_t RSVD_1389;	 // 0x15fc Reserved 1389.
	volatile uint32_t RSVD_1390;	 // 0x1600 Reserved 1390.
	volatile uint32_t RSVD_1391;	 // 0x1604 Reserved 1391.
	volatile uint32_t RSVD_1392;	 // 0x1608 Reserved 1392.
	volatile uint32_t RSVD_1393;	 // 0x160c Reserved 1393.
	volatile uint32_t RSVD_1394;	 // 0x1610 Reserved 1394.
	volatile uint32_t RSVD_1395;	 // 0x1614 Reserved 1395.
	volatile uint32_t RSVD_1396;	 // 0x1618 Reserved 1396.
	volatile uint32_t RSVD_1397;	 // 0x161c Reserved 1397.
	volatile uint32_t RSVD_1398;	 // 0x1620 Reserved 1398.
	volatile uint32_t RSVD_1399;	 // 0x1624 Reserved 1399.
	volatile uint32_t RSVD_1400;	 // 0x1628 Reserved 1400.
	volatile uint32_t RSVD_1401;	 // 0x162c Reserved 1401.
	volatile uint32_t RSVD_1402;	 // 0x1630 Reserved 1402.
	volatile uint32_t RSVD_1403;	 // 0x1634 Reserved 1403.
	volatile uint32_t RSVD_1404;	 // 0x1638 Reserved 1404.
	volatile uint32_t RSVD_1405;	 // 0x163c Reserved 1405.
	volatile uint32_t RSVD_1406;	 // 0x1640 Reserved 1406.
	volatile uint32_t RSVD_1407;	 // 0x1644 Reserved 1407.
	volatile uint32_t RSVD_1408;	 // 0x1648 Reserved 1408.
	volatile uint32_t RSVD_1409;	 // 0x164c Reserved 1409.
	volatile uint32_t RSVD_1410;	 // 0x1650 Reserved 1410.
	volatile uint32_t RSVD_1411;	 // 0x1654 Reserved 1411.
	volatile uint32_t RSVD_1412;	 // 0x1658 Reserved 1412.
	volatile uint32_t RSVD_1413;	 // 0x165c Reserved 1413.
	volatile uint32_t RSVD_1414;	 // 0x1660 Reserved 1414.
	volatile uint32_t RSVD_1415;	 // 0x1664 Reserved 1415.
	volatile uint32_t RSVD_1416;	 // 0x1668 Reserved 1416.
	volatile uint32_t RSVD_1417;	 // 0x166c Reserved 1417.
	volatile uint32_t RSVD_1418;	 // 0x1670 Reserved 1418.
	volatile uint32_t RSVD_1419;	 // 0x1674 Reserved 1419.
	volatile uint32_t RSVD_1420;	 // 0x1678 Reserved 1420.
	volatile uint32_t RSVD_1421;	 // 0x167c Reserved 1421.
	volatile uint32_t RSVD_1422;	 // 0x1680 Reserved 1422.
	volatile uint32_t RSVD_1423;	 // 0x1684 Reserved 1423.
	volatile uint32_t RSVD_1424;	 // 0x1688 Reserved 1424.
	volatile uint32_t RSVD_1425;	 // 0x168c Reserved 1425.
	volatile uint32_t RSVD_1426;	 // 0x1690 Reserved 1426.
	volatile uint32_t RSVD_1427;	 // 0x1694 Reserved 1427.
	volatile uint32_t RSVD_1428;	 // 0x1698 Reserved 1428.
	volatile uint32_t RSVD_1429;	 // 0x169c Reserved 1429.
	volatile uint32_t RSVD_1430;	 // 0x16a0 Reserved 1430.
	volatile uint32_t RSVD_1431;	 // 0x16a4 Reserved 1431.
	volatile uint32_t RSVD_1432;	 // 0x16a8 Reserved 1432.
	volatile uint32_t RSVD_1433;	 // 0x16ac Reserved 1433.
	volatile uint32_t RSVD_1434;	 // 0x16b0 Reserved 1434.
	volatile uint32_t RSVD_1435;	 // 0x16b4 Reserved 1435.
	volatile uint32_t RSVD_1436;	 // 0x16b8 Reserved 1436.
	volatile uint32_t RSVD_1437;	 // 0x16bc Reserved 1437.
	volatile uint32_t RSVD_1438;	 // 0x16c0 Reserved 1438.
	volatile uint32_t RSVD_1439;	 // 0x16c4 Reserved 1439.
	volatile uint32_t RSVD_1440;	 // 0x16c8 Reserved 1440.
	volatile uint32_t RSVD_1441;	 // 0x16cc Reserved 1441.
	volatile uint32_t RSVD_1442;	 // 0x16d0 Reserved 1442.
	volatile uint32_t RSVD_1443;	 // 0x16d4 Reserved 1443.
	volatile uint32_t RSVD_1444;	 // 0x16d8 Reserved 1444.
	volatile uint32_t RSVD_1445;	 // 0x16dc Reserved 1445.
	volatile uint32_t RSVD_1446;	 // 0x16e0 Reserved 1446.
	volatile uint32_t RSVD_1447;	 // 0x16e4 Reserved 1447.
	volatile uint32_t RSVD_1448;	 // 0x16e8 Reserved 1448.
	volatile uint32_t RSVD_1449;	 // 0x16ec Reserved 1449.
	volatile uint32_t RSVD_1450;	 // 0x16f0 Reserved 1450.
	volatile uint32_t RSVD_1451;	 // 0x16f4 Reserved 1451.
	volatile uint32_t RSVD_1452;	 // 0x16f8 Reserved 1452.
	volatile uint32_t RSVD_1453;	 // 0x16fc Reserved 1453.
	volatile uint32_t RSVD_1454;	 // 0x1700 Reserved 1454.
	volatile uint32_t RSVD_1455;	 // 0x1704 Reserved 1455.
	volatile uint32_t RSVD_1456;	 // 0x1708 Reserved 1456.
	volatile uint32_t RSVD_1457;	 // 0x170c Reserved 1457.
	volatile uint32_t RSVD_1458;	 // 0x1710 Reserved 1458.
	volatile uint32_t RSVD_1459;	 // 0x1714 Reserved 1459.
	volatile uint32_t RSVD_1460;	 // 0x1718 Reserved 1460.
	volatile uint32_t RSVD_1461;	 // 0x171c Reserved 1461.
	volatile uint32_t RSVD_1462;	 // 0x1720 Reserved 1462.
	volatile uint32_t RSVD_1463;	 // 0x1724 Reserved 1463.
	volatile uint32_t RSVD_1464;	 // 0x1728 Reserved 1464.
	volatile uint32_t RSVD_1465;	 // 0x172c Reserved 1465.
	volatile uint32_t RSVD_1466;	 // 0x1730 Reserved 1466.
	volatile uint32_t RSVD_1467;	 // 0x1734 Reserved 1467.
	volatile uint32_t RSVD_1468;	 // 0x1738 Reserved 1468.
	volatile uint32_t RSVD_1469;	 // 0x173c Reserved 1469.
	volatile uint32_t RSVD_1470;	 // 0x1740 Reserved 1470.
	volatile uint32_t RSVD_1471;	 // 0x1744 Reserved 1471.
	volatile uint32_t RSVD_1472;	 // 0x1748 Reserved 1472.
	volatile uint32_t RSVD_1473;	 // 0x174c Reserved 1473.
	volatile uint32_t RSVD_1474;	 // 0x1750 Reserved 1474.
	volatile uint32_t RSVD_1475;	 // 0x1754 Reserved 1475.
	volatile uint32_t RSVD_1476;	 // 0x1758 Reserved 1476.
	volatile uint32_t RSVD_1477;	 // 0x175c Reserved 1477.
	volatile uint32_t RSVD_1478;	 // 0x1760 Reserved 1478.
	volatile uint32_t RSVD_1479;	 // 0x1764 Reserved 1479.
	volatile uint32_t RSVD_1480;	 // 0x1768 Reserved 1480.
	volatile uint32_t RSVD_1481;	 // 0x176c Reserved 1481.
	volatile uint32_t RSVD_1482;	 // 0x1770 Reserved 1482.
	volatile uint32_t RSVD_1483;	 // 0x1774 Reserved 1483.
	volatile uint32_t RSVD_1484;	 // 0x1778 Reserved 1484.
	volatile uint32_t RSVD_1485;	 // 0x177c Reserved 1485.
	volatile uint32_t RSVD_1486;	 // 0x1780 Reserved 1486.
	volatile uint32_t RSVD_1487;	 // 0x1784 Reserved 1487.
	volatile uint32_t RSVD_1488;	 // 0x1788 Reserved 1488.
	volatile uint32_t RSVD_1489;	 // 0x178c Reserved 1489.
	volatile uint32_t RSVD_1490;	 // 0x1790 Reserved 1490.
	volatile uint32_t RSVD_1491;	 // 0x1794 Reserved 1491.
	volatile uint32_t RSVD_1492;	 // 0x1798 Reserved 1492.
	volatile uint32_t RSVD_1493;	 // 0x179c Reserved 1493.
	volatile uint32_t RSVD_1494;	 // 0x17a0 Reserved 1494.
	volatile uint32_t RSVD_1495;	 // 0x17a4 Reserved 1495.
	volatile uint32_t RSVD_1496;	 // 0x17a8 Reserved 1496.
	volatile uint32_t RSVD_1497;	 // 0x17ac Reserved 1497.
	volatile uint32_t RSVD_1498;	 // 0x17b0 Reserved 1498.
	volatile uint32_t RSVD_1499;	 // 0x17b4 Reserved 1499.
	volatile uint32_t RSVD_1500;	 // 0x17b8 Reserved 1500.
	volatile uint32_t RSVD_1501;	 // 0x17bc Reserved 1501.
	volatile uint32_t RSVD_1502;	 // 0x17c0 Reserved 1502.
	volatile uint32_t RSVD_1503;	 // 0x17c4 Reserved 1503.
	volatile uint32_t RSVD_1504;	 // 0x17c8 Reserved 1504.
	volatile uint32_t RSVD_1505;	 // 0x17cc Reserved 1505.
	volatile uint32_t RSVD_1506;	 // 0x17d0 Reserved 1506.
	volatile uint32_t RSVD_1507;	 // 0x17d4 Reserved 1507.
	volatile uint32_t RSVD_1508;	 // 0x17d8 Reserved 1508.
	volatile uint32_t RSVD_1509;	 // 0x17dc Reserved 1509.
	volatile uint32_t RSVD_1510;	 // 0x17e0 Reserved 1510.
	volatile uint32_t RSVD_1511;	 // 0x17e4 Reserved 1511.
	volatile uint32_t RSVD_1512;	 // 0x17e8 Reserved 1512.
	volatile uint32_t RSVD_1513;	 // 0x17ec Reserved 1513.
	volatile uint32_t RSVD_1514;	 // 0x17f0 Reserved 1514.
	volatile uint32_t RSVD_1515;	 // 0x17f4 Reserved 1515.
	volatile uint32_t RSVD_1516;	 // 0x17f8 Reserved 1516.
	volatile uint32_t RSVD_1517;	 // 0x17fc Reserved 1517.
	volatile uint32_t RSVD_1518;	 // 0x1800 Reserved 1518.
	volatile uint32_t RSVD_1519;	 // 0x1804 Reserved 1519.
	volatile uint32_t RSVD_1520;	 // 0x1808 Reserved 1520.
	volatile uint32_t RSVD_1521;	 // 0x180c Reserved 1521.
	volatile uint32_t RSVD_1522;	 // 0x1810 Reserved 1522.
	volatile uint32_t RSVD_1523;	 // 0x1814 Reserved 1523.
	volatile uint32_t RSVD_1524;	 // 0x1818 Reserved 1524.
	volatile uint32_t RSVD_1525;	 // 0x181c Reserved 1525.
	volatile uint32_t RSVD_1526;	 // 0x1820 Reserved 1526.
	volatile uint32_t RSVD_1527;	 // 0x1824 Reserved 1527.
	volatile uint32_t RSVD_1528;	 // 0x1828 Reserved 1528.
	volatile uint32_t RSVD_1529;	 // 0x182c Reserved 1529.
	volatile uint32_t RSVD_1530;	 // 0x1830 Reserved 1530.
	volatile uint32_t RSVD_1531;	 // 0x1834 Reserved 1531.
	volatile uint32_t RSVD_1532;	 // 0x1838 Reserved 1532.
	volatile uint32_t RSVD_1533;	 // 0x183c Reserved 1533.
	volatile uint32_t RSVD_1534;	 // 0x1840 Reserved 1534.
	volatile uint32_t RSVD_1535;	 // 0x1844 Reserved 1535.
	volatile uint32_t RSVD_1536;	 // 0x1848 Reserved 1536.
	volatile uint32_t RSVD_1537;	 // 0x184c Reserved 1537.
	volatile uint32_t RSVD_1538;	 // 0x1850 Reserved 1538.
	volatile uint32_t RSVD_1539;	 // 0x1854 Reserved 1539.
	volatile uint32_t RSVD_1540;	 // 0x1858 Reserved 1540.
	volatile uint32_t RSVD_1541;	 // 0x185c Reserved 1541.
	volatile uint32_t RSVD_1542;	 // 0x1860 Reserved 1542.
	volatile uint32_t RSVD_1543;	 // 0x1864 Reserved 1543.
	volatile uint32_t RSVD_1544;	 // 0x1868 Reserved 1544.
	volatile uint32_t RSVD_1545;	 // 0x186c Reserved 1545.
	volatile uint32_t RSVD_1546;	 // 0x1870 Reserved 1546.
	volatile uint32_t RSVD_1547;	 // 0x1874 Reserved 1547.
	volatile uint32_t RSVD_1548;	 // 0x1878 Reserved 1548.
	volatile uint32_t RSVD_1549;	 // 0x187c Reserved 1549.
	volatile uint32_t RSVD_1550;	 // 0x1880 Reserved 1550.
	volatile uint32_t RSVD_1551;	 // 0x1884 Reserved 1551.
	volatile uint32_t RSVD_1552;	 // 0x1888 Reserved 1552.
	volatile uint32_t RSVD_1553;	 // 0x188c Reserved 1553.
	volatile uint32_t RSVD_1554;	 // 0x1890 Reserved 1554.
	volatile uint32_t RSVD_1555;	 // 0x1894 Reserved 1555.
	volatile uint32_t RSVD_1556;	 // 0x1898 Reserved 1556.
	volatile uint32_t RSVD_1557;	 // 0x189c Reserved 1557.
	volatile uint32_t RSVD_1558;	 // 0x18a0 Reserved 1558.
	volatile uint32_t RSVD_1559;	 // 0x18a4 Reserved 1559.
	volatile uint32_t RSVD_1560;	 // 0x18a8 Reserved 1560.
	volatile uint32_t RSVD_1561;	 // 0x18ac Reserved 1561.
	volatile uint32_t RSVD_1562;	 // 0x18b0 Reserved 1562.
	volatile uint32_t RSVD_1563;	 // 0x18b4 Reserved 1563.
	volatile uint32_t RSVD_1564;	 // 0x18b8 Reserved 1564.
	volatile uint32_t RSVD_1565;	 // 0x18bc Reserved 1565.
	volatile uint32_t RSVD_1566;	 // 0x18c0 Reserved 1566.
	volatile uint32_t RSVD_1567;	 // 0x18c4 Reserved 1567.
	volatile uint32_t RSVD_1568;	 // 0x18c8 Reserved 1568.
	volatile uint32_t RSVD_1569;	 // 0x18cc Reserved 1569.
	volatile uint32_t RSVD_1570;	 // 0x18d0 Reserved 1570.
	volatile uint32_t RSVD_1571;	 // 0x18d4 Reserved 1571.
	volatile uint32_t RSVD_1572;	 // 0x18d8 Reserved 1572.
	volatile uint32_t RSVD_1573;	 // 0x18dc Reserved 1573.
	volatile uint32_t RSVD_1574;	 // 0x18e0 Reserved 1574.
	volatile uint32_t RSVD_1575;	 // 0x18e4 Reserved 1575.
	volatile uint32_t RSVD_1576;	 // 0x18e8 Reserved 1576.
	volatile uint32_t RSVD_1577;	 // 0x18ec Reserved 1577.
	volatile uint32_t RSVD_1578;	 // 0x18f0 Reserved 1578.
	volatile uint32_t RSVD_1579;	 // 0x18f4 Reserved 1579.
	volatile uint32_t RSVD_1580;	 // 0x18f8 Reserved 1580.
	volatile uint32_t RSVD_1581;	 // 0x18fc Reserved 1581.
	volatile uint32_t RSVD_1582;	 // 0x1900 Reserved 1582.
	volatile uint32_t RSVD_1583;	 // 0x1904 Reserved 1583.
	volatile uint32_t RSVD_1584;	 // 0x1908 Reserved 1584.
	volatile uint32_t RSVD_1585;	 // 0x190c Reserved 1585.
	volatile uint32_t RSVD_1586;	 // 0x1910 Reserved 1586.
	volatile uint32_t RSVD_1587;	 // 0x1914 Reserved 1587.
	volatile uint32_t RSVD_1588;	 // 0x1918 Reserved 1588.
	volatile uint32_t RSVD_1589;	 // 0x191c Reserved 1589.
	volatile uint32_t RSVD_1590;	 // 0x1920 Reserved 1590.
	volatile uint32_t RSVD_1591;	 // 0x1924 Reserved 1591.
	volatile uint32_t RSVD_1592;	 // 0x1928 Reserved 1592.
	volatile uint32_t RSVD_1593;	 // 0x192c Reserved 1593.
	volatile uint32_t RSVD_1594;	 // 0x1930 Reserved 1594.
	volatile uint32_t RSVD_1595;	 // 0x1934 Reserved 1595.
	volatile uint32_t RSVD_1596;	 // 0x1938 Reserved 1596.
	volatile uint32_t RSVD_1597;	 // 0x193c Reserved 1597.
	volatile uint32_t RSVD_1598;	 // 0x1940 Reserved 1598.
	volatile uint32_t RSVD_1599;	 // 0x1944 Reserved 1599.
	volatile uint32_t RSVD_1600;	 // 0x1948 Reserved 1600.
	volatile uint32_t RSVD_1601;	 // 0x194c Reserved 1601.
	volatile uint32_t RSVD_1602;	 // 0x1950 Reserved 1602.
	volatile uint32_t RSVD_1603;	 // 0x1954 Reserved 1603.
	volatile uint32_t RSVD_1604;	 // 0x1958 Reserved 1604.
	volatile uint32_t RSVD_1605;	 // 0x195c Reserved 1605.
	volatile uint32_t RSVD_1606;	 // 0x1960 Reserved 1606.
	volatile uint32_t RSVD_1607;	 // 0x1964 Reserved 1607.
	volatile uint32_t RSVD_1608;	 // 0x1968 Reserved 1608.
	volatile uint32_t RSVD_1609;	 // 0x196c Reserved 1609.
	volatile uint32_t RSVD_1610;	 // 0x1970 Reserved 1610.
	volatile uint32_t RSVD_1611;	 // 0x1974 Reserved 1611.
	volatile uint32_t RSVD_1612;	 // 0x1978 Reserved 1612.
	volatile uint32_t RSVD_1613;	 // 0x197c Reserved 1613.
	volatile uint32_t RSVD_1614;	 // 0x1980 Reserved 1614.
	volatile uint32_t RSVD_1615;	 // 0x1984 Reserved 1615.
	volatile uint32_t RSVD_1616;	 // 0x1988 Reserved 1616.
	volatile uint32_t RSVD_1617;	 // 0x198c Reserved 1617.
	volatile uint32_t RSVD_1618;	 // 0x1990 Reserved 1618.
	volatile uint32_t RSVD_1619;	 // 0x1994 Reserved 1619.
	volatile uint32_t RSVD_1620;	 // 0x1998 Reserved 1620.
	volatile uint32_t RSVD_1621;	 // 0x199c Reserved 1621.
	volatile uint32_t RSVD_1622;	 // 0x19a0 Reserved 1622.
	volatile uint32_t RSVD_1623;	 // 0x19a4 Reserved 1623.
	volatile uint32_t RSVD_1624;	 // 0x19a8 Reserved 1624.
	volatile uint32_t RSVD_1625;	 // 0x19ac Reserved 1625.
	volatile uint32_t RSVD_1626;	 // 0x19b0 Reserved 1626.
	volatile uint32_t RSVD_1627;	 // 0x19b4 Reserved 1627.
	volatile uint32_t RSVD_1628;	 // 0x19b8 Reserved 1628.
	volatile uint32_t RSVD_1629;	 // 0x19bc Reserved 1629.
	volatile uint32_t RSVD_1630;	 // 0x19c0 Reserved 1630.
	volatile uint32_t RSVD_1631;	 // 0x19c4 Reserved 1631.
	volatile uint32_t RSVD_1632;	 // 0x19c8 Reserved 1632.
	volatile uint32_t RSVD_1633;	 // 0x19cc Reserved 1633.
	volatile uint32_t RSVD_1634;	 // 0x19d0 Reserved 1634.
	volatile uint32_t RSVD_1635;	 // 0x19d4 Reserved 1635.
	volatile uint32_t RSVD_1636;	 // 0x19d8 Reserved 1636.
	volatile uint32_t RSVD_1637;	 // 0x19dc Reserved 1637.
	volatile uint32_t RSVD_1638;	 // 0x19e0 Reserved 1638.
	volatile uint32_t RSVD_1639;	 // 0x19e4 Reserved 1639.
	volatile uint32_t RSVD_1640;	 // 0x19e8 Reserved 1640.
	volatile uint32_t RSVD_1641;	 // 0x19ec Reserved 1641.
	volatile uint32_t RSVD_1642;	 // 0x19f0 Reserved 1642.
	volatile uint32_t RSVD_1643;	 // 0x19f4 Reserved 1643.
	volatile uint32_t RSVD_1644;	 // 0x19f8 Reserved 1644.
	volatile uint32_t RSVD_1645;	 // 0x19fc Reserved 1645.
	volatile uint32_t RSVD_1646;	 // 0x1a00 Reserved 1646.
	volatile uint32_t RSVD_1647;	 // 0x1a04 Reserved 1647.
	volatile uint32_t RSVD_1648;	 // 0x1a08 Reserved 1648.
	volatile uint32_t RSVD_1649;	 // 0x1a0c Reserved 1649.
	volatile uint32_t RSVD_1650;	 // 0x1a10 Reserved 1650.
	volatile uint32_t RSVD_1651;	 // 0x1a14 Reserved 1651.
	volatile uint32_t RSVD_1652;	 // 0x1a18 Reserved 1652.
	volatile uint32_t RSVD_1653;	 // 0x1a1c Reserved 1653.
	volatile uint32_t RSVD_1654;	 // 0x1a20 Reserved 1654.
	volatile uint32_t RSVD_1655;	 // 0x1a24 Reserved 1655.
	volatile uint32_t RSVD_1656;	 // 0x1a28 Reserved 1656.
	volatile uint32_t RSVD_1657;	 // 0x1a2c Reserved 1657.
	volatile uint32_t RSVD_1658;	 // 0x1a30 Reserved 1658.
	volatile uint32_t RSVD_1659;	 // 0x1a34 Reserved 1659.
	volatile uint32_t RSVD_1660;	 // 0x1a38 Reserved 1660.
	volatile uint32_t RSVD_1661;	 // 0x1a3c Reserved 1661.
	volatile uint32_t RSVD_1662;	 // 0x1a40 Reserved 1662.
	volatile uint32_t RSVD_1663;	 // 0x1a44 Reserved 1663.
	volatile uint32_t RSVD_1664;	 // 0x1a48 Reserved 1664.
	volatile uint32_t RSVD_1665;	 // 0x1a4c Reserved 1665.
	volatile uint32_t RSVD_1666;	 // 0x1a50 Reserved 1666.
	volatile uint32_t RSVD_1667;	 // 0x1a54 Reserved 1667.
	volatile uint32_t RSVD_1668;	 // 0x1a58 Reserved 1668.
	volatile uint32_t RSVD_1669;	 // 0x1a5c Reserved 1669.
	volatile uint32_t RSVD_1670;	 // 0x1a60 Reserved 1670.
	volatile uint32_t RSVD_1671;	 // 0x1a64 Reserved 1671.
	volatile uint32_t RSVD_1672;	 // 0x1a68 Reserved 1672.
	volatile uint32_t RSVD_1673;	 // 0x1a6c Reserved 1673.
	volatile uint32_t RSVD_1674;	 // 0x1a70 Reserved 1674.
	volatile uint32_t RSVD_1675;	 // 0x1a74 Reserved 1675.
	volatile uint32_t RSVD_1676;	 // 0x1a78 Reserved 1676.
	volatile uint32_t RSVD_1677;	 // 0x1a7c Reserved 1677.
	volatile uint32_t RSVD_1678;	 // 0x1a80 Reserved 1678.
	volatile uint32_t RSVD_1679;	 // 0x1a84 Reserved 1679.
	volatile uint32_t RSVD_1680;	 // 0x1a88 Reserved 1680.
	volatile uint32_t RSVD_1681;	 // 0x1a8c Reserved 1681.
	volatile uint32_t RSVD_1682;	 // 0x1a90 Reserved 1682.
	volatile uint32_t RSVD_1683;	 // 0x1a94 Reserved 1683.
	volatile uint32_t RSVD_1684;	 // 0x1a98 Reserved 1684.
	volatile uint32_t RSVD_1685;	 // 0x1a9c Reserved 1685.
	volatile uint32_t RSVD_1686;	 // 0x1aa0 Reserved 1686.
	volatile uint32_t RSVD_1687;	 // 0x1aa4 Reserved 1687.
	volatile uint32_t RSVD_1688;	 // 0x1aa8 Reserved 1688.
	volatile uint32_t RSVD_1689;	 // 0x1aac Reserved 1689.
	volatile uint32_t RSVD_1690;	 // 0x1ab0 Reserved 1690.
	volatile uint32_t RSVD_1691;	 // 0x1ab4 Reserved 1691.
	volatile uint32_t RSVD_1692;	 // 0x1ab8 Reserved 1692.
	volatile uint32_t RSVD_1693;	 // 0x1abc Reserved 1693.
	volatile uint32_t RSVD_1694;	 // 0x1ac0 Reserved 1694.
	volatile uint32_t RSVD_1695;	 // 0x1ac4 Reserved 1695.
	volatile uint32_t RSVD_1696;	 // 0x1ac8 Reserved 1696.
	volatile uint32_t RSVD_1697;	 // 0x1acc Reserved 1697.
	volatile uint32_t RSVD_1698;	 // 0x1ad0 Reserved 1698.
	volatile uint32_t RSVD_1699;	 // 0x1ad4 Reserved 1699.
	volatile uint32_t RSVD_1700;	 // 0x1ad8 Reserved 1700.
	volatile uint32_t RSVD_1701;	 // 0x1adc Reserved 1701.
	volatile uint32_t RSVD_1702;	 // 0x1ae0 Reserved 1702.
	volatile uint32_t RSVD_1703;	 // 0x1ae4 Reserved 1703.
	volatile uint32_t RSVD_1704;	 // 0x1ae8 Reserved 1704.
	volatile uint32_t RSVD_1705;	 // 0x1aec Reserved 1705.
	volatile uint32_t RSVD_1706;	 // 0x1af0 Reserved 1706.
	volatile uint32_t RSVD_1707;	 // 0x1af4 Reserved 1707.
	volatile uint32_t RSVD_1708;	 // 0x1af8 Reserved 1708.
	volatile uint32_t RSVD_1709;	 // 0x1afc Reserved 1709.
	volatile uint32_t RSVD_1710;	 // 0x1b00 Reserved 1710.
	volatile uint32_t RSVD_1711;	 // 0x1b04 Reserved 1711.
	volatile uint32_t RSVD_1712;	 // 0x1b08 Reserved 1712.
	volatile uint32_t RSVD_1713;	 // 0x1b0c Reserved 1713.
	volatile uint32_t RSVD_1714;	 // 0x1b10 Reserved 1714.
	volatile uint32_t RSVD_1715;	 // 0x1b14 Reserved 1715.
	volatile uint32_t RSVD_1716;	 // 0x1b18 Reserved 1716.
	volatile uint32_t RSVD_1717;	 // 0x1b1c Reserved 1717.
	volatile uint32_t RSVD_1718;	 // 0x1b20 Reserved 1718.
	volatile uint32_t RSVD_1719;	 // 0x1b24 Reserved 1719.
	volatile uint32_t RSVD_1720;	 // 0x1b28 Reserved 1720.
	volatile uint32_t RSVD_1721;	 // 0x1b2c Reserved 1721.
	volatile uint32_t RSVD_1722;	 // 0x1b30 Reserved 1722.
	volatile uint32_t RSVD_1723;	 // 0x1b34 Reserved 1723.
	volatile uint32_t RSVD_1724;	 // 0x1b38 Reserved 1724.
	volatile uint32_t RSVD_1725;	 // 0x1b3c Reserved 1725.
	volatile uint32_t RSVD_1726;	 // 0x1b40 Reserved 1726.
	volatile uint32_t RSVD_1727;	 // 0x1b44 Reserved 1727.
	volatile uint32_t RSVD_1728;	 // 0x1b48 Reserved 1728.
	volatile uint32_t RSVD_1729;	 // 0x1b4c Reserved 1729.
	volatile uint32_t RSVD_1730;	 // 0x1b50 Reserved 1730.
	volatile uint32_t RSVD_1731;	 // 0x1b54 Reserved 1731.
	volatile uint32_t RSVD_1732;	 // 0x1b58 Reserved 1732.
	volatile uint32_t RSVD_1733;	 // 0x1b5c Reserved 1733.
	volatile uint32_t RSVD_1734;	 // 0x1b60 Reserved 1734.
	volatile uint32_t RSVD_1735;	 // 0x1b64 Reserved 1735.
	volatile uint32_t RSVD_1736;	 // 0x1b68 Reserved 1736.
	volatile uint32_t RSVD_1737;	 // 0x1b6c Reserved 1737.
	volatile uint32_t RSVD_1738;	 // 0x1b70 Reserved 1738.
	volatile uint32_t RSVD_1739;	 // 0x1b74 Reserved 1739.
	volatile uint32_t RSVD_1740;	 // 0x1b78 Reserved 1740.
	volatile uint32_t RSVD_1741;	 // 0x1b7c Reserved 1741.
	volatile uint32_t RSVD_1742;	 // 0x1b80 Reserved 1742.
	volatile uint32_t RSVD_1743;	 // 0x1b84 Reserved 1743.
	volatile uint32_t RSVD_1744;	 // 0x1b88 Reserved 1744.
	volatile uint32_t RSVD_1745;	 // 0x1b8c Reserved 1745.
	volatile uint32_t RSVD_1746;	 // 0x1b90 Reserved 1746.
	volatile uint32_t RSVD_1747;	 // 0x1b94 Reserved 1747.
	volatile uint32_t RSVD_1748;	 // 0x1b98 Reserved 1748.
	volatile uint32_t RSVD_1749;	 // 0x1b9c Reserved 1749.
	volatile uint32_t RSVD_1750;	 // 0x1ba0 Reserved 1750.
	volatile uint32_t RSVD_1751;	 // 0x1ba4 Reserved 1751.
	volatile uint32_t RSVD_1752;	 // 0x1ba8 Reserved 1752.
	volatile uint32_t RSVD_1753;	 // 0x1bac Reserved 1753.
	volatile uint32_t RSVD_1754;	 // 0x1bb0 Reserved 1754.
	volatile uint32_t RSVD_1755;	 // 0x1bb4 Reserved 1755.
	volatile uint32_t RSVD_1756;	 // 0x1bb8 Reserved 1756.
	volatile uint32_t RSVD_1757;	 // 0x1bbc Reserved 1757.
	volatile uint32_t RSVD_1758;	 // 0x1bc0 Reserved 1758.
	volatile uint32_t RSVD_1759;	 // 0x1bc4 Reserved 1759.
	volatile uint32_t RSVD_1760;	 // 0x1bc8 Reserved 1760.
	volatile uint32_t RSVD_1761;	 // 0x1bcc Reserved 1761.
	volatile uint32_t RSVD_1762;	 // 0x1bd0 Reserved 1762.
	volatile uint32_t RSVD_1763;	 // 0x1bd4 Reserved 1763.
	volatile uint32_t RSVD_1764;	 // 0x1bd8 Reserved 1764.
	volatile uint32_t RSVD_1765;	 // 0x1bdc Reserved 1765.
	volatile uint32_t RSVD_1766;	 // 0x1be0 Reserved 1766.
	volatile uint32_t RSVD_1767;	 // 0x1be4 Reserved 1767.
	volatile uint32_t RSVD_1768;	 // 0x1be8 Reserved 1768.
	volatile uint32_t RSVD_1769;	 // 0x1bec Reserved 1769.
	volatile uint32_t RSVD_1770;	 // 0x1bf0 Reserved 1770.
	volatile uint32_t RSVD_1771;	 // 0x1bf4 Reserved 1771.
	volatile uint32_t RSVD_1772;	 // 0x1bf8 Reserved 1772.
	volatile uint32_t RSVD_1773;	 // 0x1bfc Reserved 1773.
	volatile uint32_t RSVD_1774;	 // 0x1c00 Reserved 1774.
	volatile uint32_t RSVD_1775;	 // 0x1c04 Reserved 1775.
	volatile uint32_t RSVD_1776;	 // 0x1c08 Reserved 1776.
	volatile uint32_t RSVD_1777;	 // 0x1c0c Reserved 1777.
	volatile uint32_t RSVD_1778;	 // 0x1c10 Reserved 1778.
	volatile uint32_t RSVD_1779;	 // 0x1c14 Reserved 1779.
	volatile uint32_t RSVD_1780;	 // 0x1c18 Reserved 1780.
	volatile uint32_t RSVD_1781;	 // 0x1c1c Reserved 1781.
	volatile uint32_t RSVD_1782;	 // 0x1c20 Reserved 1782.
	volatile uint32_t RSVD_1783;	 // 0x1c24 Reserved 1783.
	volatile uint32_t RSVD_1784;	 // 0x1c28 Reserved 1784.
	volatile uint32_t RSVD_1785;	 // 0x1c2c Reserved 1785.
	volatile uint32_t RSVD_1786;	 // 0x1c30 Reserved 1786.
	volatile uint32_t RSVD_1787;	 // 0x1c34 Reserved 1787.
	volatile uint32_t RSVD_1788;	 // 0x1c38 Reserved 1788.
	volatile uint32_t RSVD_1789;	 // 0x1c3c Reserved 1789.
	volatile uint32_t RSVD_1790;	 // 0x1c40 Reserved 1790.
	volatile uint32_t RSVD_1791;	 // 0x1c44 Reserved 1791.
	volatile uint32_t RSVD_1792;	 // 0x1c48 Reserved 1792.
	volatile uint32_t RSVD_1793;	 // 0x1c4c Reserved 1793.
	volatile uint32_t RSVD_1794;	 // 0x1c50 Reserved 1794.
	volatile uint32_t RSVD_1795;	 // 0x1c54 Reserved 1795.
	volatile uint32_t RSVD_1796;	 // 0x1c58 Reserved 1796.
	volatile uint32_t RSVD_1797;	 // 0x1c5c Reserved 1797.
	volatile uint32_t RSVD_1798;	 // 0x1c60 Reserved 1798.
	volatile uint32_t RSVD_1799;	 // 0x1c64 Reserved 1799.
	volatile uint32_t RSVD_1800;	 // 0x1c68 Reserved 1800.
	volatile uint32_t RSVD_1801;	 // 0x1c6c Reserved 1801.
	volatile uint32_t RSVD_1802;	 // 0x1c70 Reserved 1802.
	volatile uint32_t RSVD_1803;	 // 0x1c74 Reserved 1803.
	volatile uint32_t RSVD_1804;	 // 0x1c78 Reserved 1804.
	volatile uint32_t RSVD_1805;	 // 0x1c7c Reserved 1805.
	volatile uint32_t RSVD_1806;	 // 0x1c80 Reserved 1806.
	volatile uint32_t RSVD_1807;	 // 0x1c84 Reserved 1807.
	volatile uint32_t RSVD_1808;	 // 0x1c88 Reserved 1808.
	volatile uint32_t RSVD_1809;	 // 0x1c8c Reserved 1809.
	volatile uint32_t RSVD_1810;	 // 0x1c90 Reserved 1810.
	volatile uint32_t RSVD_1811;	 // 0x1c94 Reserved 1811.
	volatile uint32_t RSVD_1812;	 // 0x1c98 Reserved 1812.
	volatile uint32_t RSVD_1813;	 // 0x1c9c Reserved 1813.
	volatile uint32_t RSVD_1814;	 // 0x1ca0 Reserved 1814.
	volatile uint32_t RSVD_1815;	 // 0x1ca4 Reserved 1815.
	volatile uint32_t RSVD_1816;	 // 0x1ca8 Reserved 1816.
	volatile uint32_t RSVD_1817;	 // 0x1cac Reserved 1817.
	volatile uint32_t RSVD_1818;	 // 0x1cb0 Reserved 1818.
	volatile uint32_t RSVD_1819;	 // 0x1cb4 Reserved 1819.
	volatile uint32_t RSVD_1820;	 // 0x1cb8 Reserved 1820.
	volatile uint32_t RSVD_1821;	 // 0x1cbc Reserved 1821.
	volatile uint32_t RSVD_1822;	 // 0x1cc0 Reserved 1822.
	volatile uint32_t RSVD_1823;	 // 0x1cc4 Reserved 1823.
	volatile uint32_t RSVD_1824;	 // 0x1cc8 Reserved 1824.
	volatile uint32_t RSVD_1825;	 // 0x1ccc Reserved 1825.
	volatile uint32_t RSVD_1826;	 // 0x1cd0 Reserved 1826.
	volatile uint32_t RSVD_1827;	 // 0x1cd4 Reserved 1827.
	volatile uint32_t RSVD_1828;	 // 0x1cd8 Reserved 1828.
	volatile uint32_t RSVD_1829;	 // 0x1cdc Reserved 1829.
	volatile uint32_t RSVD_1830;	 // 0x1ce0 Reserved 1830.
	volatile uint32_t RSVD_1831;	 // 0x1ce4 Reserved 1831.
	volatile uint32_t RSVD_1832;	 // 0x1ce8 Reserved 1832.
	volatile uint32_t RSVD_1833;	 // 0x1cec Reserved 1833.
	volatile uint32_t RSVD_1834;	 // 0x1cf0 Reserved 1834.
	volatile uint32_t RSVD_1835;	 // 0x1cf4 Reserved 1835.
	volatile uint32_t RSVD_1836;	 // 0x1cf8 Reserved 1836.
	volatile uint32_t RSVD_1837;	 // 0x1cfc Reserved 1837.
	volatile uint32_t RSVD_1838;	 // 0x1d00 Reserved 1838.
	volatile uint32_t RSVD_1839;	 // 0x1d04 Reserved 1839.
	volatile uint32_t RSVD_1840;	 // 0x1d08 Reserved 1840.
	volatile uint32_t RSVD_1841;	 // 0x1d0c Reserved 1841.
	volatile uint32_t RSVD_1842;	 // 0x1d10 Reserved 1842.
	volatile uint32_t RSVD_1843;	 // 0x1d14 Reserved 1843.
	volatile uint32_t RSVD_1844;	 // 0x1d18 Reserved 1844.
	volatile uint32_t RSVD_1845;	 // 0x1d1c Reserved 1845.
	volatile uint32_t RSVD_1846;	 // 0x1d20 Reserved 1846.
	volatile uint32_t RSVD_1847;	 // 0x1d24 Reserved 1847.
	volatile uint32_t RSVD_1848;	 // 0x1d28 Reserved 1848.
	volatile uint32_t RSVD_1849;	 // 0x1d2c Reserved 1849.
	volatile uint32_t RSVD_1850;	 // 0x1d30 Reserved 1850.
	volatile uint32_t RSVD_1851;	 // 0x1d34 Reserved 1851.
	volatile uint32_t RSVD_1852;	 // 0x1d38 Reserved 1852.
	volatile uint32_t RSVD_1853;	 // 0x1d3c Reserved 1853.
	volatile uint32_t RSVD_1854;	 // 0x1d40 Reserved 1854.
	volatile uint32_t RSVD_1855;	 // 0x1d44 Reserved 1855.
	volatile uint32_t RSVD_1856;	 // 0x1d48 Reserved 1856.
	volatile uint32_t RSVD_1857;	 // 0x1d4c Reserved 1857.
	volatile uint32_t RSVD_1858;	 // 0x1d50 Reserved 1858.
	volatile uint32_t RSVD_1859;	 // 0x1d54 Reserved 1859.
	volatile uint32_t RSVD_1860;	 // 0x1d58 Reserved 1860.
	volatile uint32_t RSVD_1861;	 // 0x1d5c Reserved 1861.
	volatile uint32_t RSVD_1862;	 // 0x1d60 Reserved 1862.
	volatile uint32_t RSVD_1863;	 // 0x1d64 Reserved 1863.
	volatile uint32_t RSVD_1864;	 // 0x1d68 Reserved 1864.
	volatile uint32_t RSVD_1865;	 // 0x1d6c Reserved 1865.
	volatile uint32_t RSVD_1866;	 // 0x1d70 Reserved 1866.
	volatile uint32_t RSVD_1867;	 // 0x1d74 Reserved 1867.
	volatile uint32_t RSVD_1868;	 // 0x1d78 Reserved 1868.
	volatile uint32_t RSVD_1869;	 // 0x1d7c Reserved 1869.
	volatile uint32_t RSVD_1870;	 // 0x1d80 Reserved 1870.
	volatile uint32_t RSVD_1871;	 // 0x1d84 Reserved 1871.
	volatile uint32_t RSVD_1872;	 // 0x1d88 Reserved 1872.
	volatile uint32_t RSVD_1873;	 // 0x1d8c Reserved 1873.
	volatile uint32_t RSVD_1874;	 // 0x1d90 Reserved 1874.
	volatile uint32_t RSVD_1875;	 // 0x1d94 Reserved 1875.
	volatile uint32_t RSVD_1876;	 // 0x1d98 Reserved 1876.
	volatile uint32_t RSVD_1877;	 // 0x1d9c Reserved 1877.
	volatile uint32_t RSVD_1878;	 // 0x1da0 Reserved 1878.
	volatile uint32_t RSVD_1879;	 // 0x1da4 Reserved 1879.
	volatile uint32_t RSVD_1880;	 // 0x1da8 Reserved 1880.
	volatile uint32_t RSVD_1881;	 // 0x1dac Reserved 1881.
	volatile uint32_t RSVD_1882;	 // 0x1db0 Reserved 1882.
	volatile uint32_t RSVD_1883;	 // 0x1db4 Reserved 1883.
	volatile uint32_t RSVD_1884;	 // 0x1db8 Reserved 1884.
	volatile uint32_t RSVD_1885;	 // 0x1dbc Reserved 1885.
	volatile uint32_t RSVD_1886;	 // 0x1dc0 Reserved 1886.
	volatile uint32_t RSVD_1887;	 // 0x1dc4 Reserved 1887.
	volatile uint32_t RSVD_1888;	 // 0x1dc8 Reserved 1888.
	volatile uint32_t RSVD_1889;	 // 0x1dcc Reserved 1889.
	volatile uint32_t RSVD_1890;	 // 0x1dd0 Reserved 1890.
	volatile uint32_t RSVD_1891;	 // 0x1dd4 Reserved 1891.
	volatile uint32_t RSVD_1892;	 // 0x1dd8 Reserved 1892.
	volatile uint32_t RSVD_1893;	 // 0x1ddc Reserved 1893.
	volatile uint32_t RSVD_1894;	 // 0x1de0 Reserved 1894.
	volatile uint32_t RSVD_1895;	 // 0x1de4 Reserved 1895.
	volatile uint32_t RSVD_1896;	 // 0x1de8 Reserved 1896.
	volatile uint32_t RSVD_1897;	 // 0x1dec Reserved 1897.
	volatile uint32_t RSVD_1898;	 // 0x1df0 Reserved 1898.
	volatile uint32_t RSVD_1899;	 // 0x1df4 Reserved 1899.
	volatile uint32_t RSVD_1900;	 // 0x1df8 Reserved 1900.
	volatile uint32_t RSVD_1901;	 // 0x1dfc Reserved 1901.
	volatile uint32_t RSVD_1902;	 // 0x1e00 Reserved 1902.
	volatile uint32_t RSVD_1903;	 // 0x1e04 Reserved 1903.
	volatile uint32_t RSVD_1904;	 // 0x1e08 Reserved 1904.
	volatile uint32_t RSVD_1905;	 // 0x1e0c Reserved 1905.
	volatile uint32_t RSVD_1906;	 // 0x1e10 Reserved 1906.
	volatile uint32_t RSVD_1907;	 // 0x1e14 Reserved 1907.
	volatile uint32_t RSVD_1908;	 // 0x1e18 Reserved 1908.
	volatile uint32_t RSVD_1909;	 // 0x1e1c Reserved 1909.
	volatile uint32_t RSVD_1910;	 // 0x1e20 Reserved 1910.
	volatile uint32_t RSVD_1911;	 // 0x1e24 Reserved 1911.
	volatile uint32_t RSVD_1912;	 // 0x1e28 Reserved 1912.
	volatile uint32_t RSVD_1913;	 // 0x1e2c Reserved 1913.
	volatile uint32_t RSVD_1914;	 // 0x1e30 Reserved 1914.
	volatile uint32_t RSVD_1915;	 // 0x1e34 Reserved 1915.
	volatile uint32_t RSVD_1916;	 // 0x1e38 Reserved 1916.
	volatile uint32_t RSVD_1917;	 // 0x1e3c Reserved 1917.
	volatile uint32_t RSVD_1918;	 // 0x1e40 Reserved 1918.
	volatile uint32_t RSVD_1919;	 // 0x1e44 Reserved 1919.
	volatile uint32_t RSVD_1920;	 // 0x1e48 Reserved 1920.
	volatile uint32_t RSVD_1921;	 // 0x1e4c Reserved 1921.
	volatile uint32_t RSVD_1922;	 // 0x1e50 Reserved 1922.
	volatile uint32_t RSVD_1923;	 // 0x1e54 Reserved 1923.
	volatile uint32_t RSVD_1924;	 // 0x1e58 Reserved 1924.
	volatile uint32_t RSVD_1925;	 // 0x1e5c Reserved 1925.
	volatile uint32_t RSVD_1926;	 // 0x1e60 Reserved 1926.
	volatile uint32_t RSVD_1927;	 // 0x1e64 Reserved 1927.
	volatile uint32_t RSVD_1928;	 // 0x1e68 Reserved 1928.
	volatile uint32_t RSVD_1929;	 // 0x1e6c Reserved 1929.
	volatile uint32_t RSVD_1930;	 // 0x1e70 Reserved 1930.
	volatile uint32_t RSVD_1931;	 // 0x1e74 Reserved 1931.
	volatile uint32_t RSVD_1932;	 // 0x1e78 Reserved 1932.
	volatile uint32_t RSVD_1933;	 // 0x1e7c Reserved 1933.
	volatile uint32_t RSVD_1934;	 // 0x1e80 Reserved 1934.
	volatile uint32_t RSVD_1935;	 // 0x1e84 Reserved 1935.
	volatile uint32_t RSVD_1936;	 // 0x1e88 Reserved 1936.
	volatile uint32_t RSVD_1937;	 // 0x1e8c Reserved 1937.
	volatile uint32_t RSVD_1938;	 // 0x1e90 Reserved 1938.
	volatile uint32_t RSVD_1939;	 // 0x1e94 Reserved 1939.
	volatile uint32_t RSVD_1940;	 // 0x1e98 Reserved 1940.
	volatile uint32_t RSVD_1941;	 // 0x1e9c Reserved 1941.
	volatile uint32_t RSVD_1942;	 // 0x1ea0 Reserved 1942.
	volatile uint32_t RSVD_1943;	 // 0x1ea4 Reserved 1943.
	volatile uint32_t RSVD_1944;	 // 0x1ea8 Reserved 1944.
	volatile uint32_t RSVD_1945;	 // 0x1eac Reserved 1945.
	volatile uint32_t RSVD_1946;	 // 0x1eb0 Reserved 1946.
	volatile uint32_t RSVD_1947;	 // 0x1eb4 Reserved 1947.
	volatile uint32_t RSVD_1948;	 // 0x1eb8 Reserved 1948.
	volatile uint32_t RSVD_1949;	 // 0x1ebc Reserved 1949.
	volatile uint32_t RSVD_1950;	 // 0x1ec0 Reserved 1950.
	volatile uint32_t RSVD_1951;	 // 0x1ec4 Reserved 1951.
	volatile uint32_t RSVD_1952;	 // 0x1ec8 Reserved 1952.
	volatile uint32_t RSVD_1953;	 // 0x1ecc Reserved 1953.
	volatile uint32_t RSVD_1954;	 // 0x1ed0 Reserved 1954.
	volatile uint32_t RSVD_1955;	 // 0x1ed4 Reserved 1955.
	volatile uint32_t RSVD_1956;	 // 0x1ed8 Reserved 1956.
	volatile uint32_t RSVD_1957;	 // 0x1edc Reserved 1957.
	volatile uint32_t RSVD_1958;	 // 0x1ee0 Reserved 1958.
	volatile uint32_t RSVD_1959;	 // 0x1ee4 Reserved 1959.
	volatile uint32_t RSVD_1960;	 // 0x1ee8 Reserved 1960.
	volatile uint32_t RSVD_1961;	 // 0x1eec Reserved 1961.
	volatile uint32_t RSVD_1962;	 // 0x1ef0 Reserved 1962.
	volatile uint32_t RSVD_1963;	 // 0x1ef4 Reserved 1963.
	volatile uint32_t RSVD_1964;	 // 0x1ef8 Reserved 1964.
	volatile uint32_t RSVD_1965;	 // 0x1efc Reserved 1965.
	volatile uint32_t RSVD_1966;	 // 0x1f00 Reserved 1966.
	volatile uint32_t RSVD_1967;	 // 0x1f04 Reserved 1967.
	volatile uint32_t RSVD_1968;	 // 0x1f08 Reserved 1968.
	volatile uint32_t RSVD_1969;	 // 0x1f0c Reserved 1969.
	volatile uint32_t RSVD_1970;	 // 0x1f10 Reserved 1970.
	volatile uint32_t RSVD_1971;	 // 0x1f14 Reserved 1971.
	volatile uint32_t RSVD_1972;	 // 0x1f18 Reserved 1972.
	volatile uint32_t RSVD_1973;	 // 0x1f1c Reserved 1973.
	volatile uint32_t RSVD_1974;	 // 0x1f20 Reserved 1974.
	volatile uint32_t RSVD_1975;	 // 0x1f24 Reserved 1975.
	volatile uint32_t RSVD_1976;	 // 0x1f28 Reserved 1976.
	volatile uint32_t RSVD_1977;	 // 0x1f2c Reserved 1977.
	volatile uint32_t RSVD_1978;	 // 0x1f30 Reserved 1978.
	volatile uint32_t RSVD_1979;	 // 0x1f34 Reserved 1979.
	volatile uint32_t RSVD_1980;	 // 0x1f38 Reserved 1980.
	volatile uint32_t RSVD_1981;	 // 0x1f3c Reserved 1981.
	volatile uint32_t RSVD_1982;	 // 0x1f40 Reserved 1982.
	volatile uint32_t RSVD_1983;	 // 0x1f44 Reserved 1983.
	volatile uint32_t RSVD_1984;	 // 0x1f48 Reserved 1984.
	volatile uint32_t RSVD_1985;	 // 0x1f4c Reserved 1985.
	volatile uint32_t RSVD_1986;	 // 0x1f50 Reserved 1986.
	volatile uint32_t RSVD_1987;	 // 0x1f54 Reserved 1987.
	volatile uint32_t RSVD_1988;	 // 0x1f58 Reserved 1988.
	volatile uint32_t RSVD_1989;	 // 0x1f5c Reserved 1989.
	volatile uint32_t RSVD_1990;	 // 0x1f60 Reserved 1990.
	volatile uint32_t RSVD_1991;	 // 0x1f64 Reserved 1991.
	volatile uint32_t RSVD_1992;	 // 0x1f68 Reserved 1992.
	volatile uint32_t RSVD_1993;	 // 0x1f6c Reserved 1993.
	volatile uint32_t RSVD_1994;	 // 0x1f70 Reserved 1994.
	volatile uint32_t RSVD_1995;	 // 0x1f74 Reserved 1995.
	volatile uint32_t RSVD_1996;	 // 0x1f78 Reserved 1996.
	volatile uint32_t RSVD_1997;	 // 0x1f7c Reserved 1997.
	volatile uint32_t RSVD_1998;	 // 0x1f80 Reserved 1998.
	volatile uint32_t RSVD_1999;	 // 0x1f84 Reserved 1999.
	volatile uint32_t RSVD_2000;	 // 0x1f88 Reserved 2000.
	volatile uint32_t RSVD_2001;	 // 0x1f8c Reserved 2001.
	volatile uint32_t RSVD_2002;	 // 0x1f90 Reserved 2002.
	volatile uint32_t RSVD_2003;	 // 0x1f94 Reserved 2003.
	volatile uint32_t RSVD_2004;	 // 0x1f98 Reserved 2004.
	volatile uint32_t RSVD_2005;	 // 0x1f9c Reserved 2005.
	volatile uint32_t RSVD_2006;	 // 0x1fa0 Reserved 2006.
	volatile uint32_t RSVD_2007;	 // 0x1fa4 Reserved 2007.
	volatile uint32_t RSVD_2008;	 // 0x1fa8 Reserved 2008.
	volatile uint32_t RSVD_2009;	 // 0x1fac Reserved 2009.
	volatile uint32_t RSVD_2010;	 // 0x1fb0 Reserved 2010.
	volatile uint32_t RSVD_2011;	 // 0x1fb4 Reserved 2011.
	volatile uint32_t RSVD_2012;	 // 0x1fb8 Reserved 2012.
	volatile uint32_t RSVD_2013;	 // 0x1fbc Reserved 2013.
	volatile uint32_t RSVD_2014;	 // 0x1fc0 Reserved 2014.
	volatile uint32_t RSVD_2015;	 // 0x1fc4 Reserved 2015.
	volatile uint32_t RSVD_2016;	 // 0x1fc8 Reserved 2016.
	volatile uint32_t RSVD_2017;	 // 0x1fcc Reserved 2017.
	volatile uint32_t RSVD_2018;	 // 0x1fd0 Reserved 2018.
	volatile uint32_t RSVD_2019;	 // 0x1fd4 Reserved 2019.
	volatile uint32_t RSVD_2020;	 // 0x1fd8 Reserved 2020.
	volatile uint32_t RSVD_2021;	 // 0x1fdc Reserved 2021.
	volatile uint32_t RSVD_2022;	 // 0x1fe0 Reserved 2022.
	volatile uint32_t RSVD_2023;	 // 0x1fe4 Reserved 2023.
	volatile uint32_t RSVD_2024;	 // 0x1fe8 Reserved 2024.
	volatile uint32_t RSVD_2025;	 // 0x1fec Reserved 2025.
	volatile uint32_t RSVD_2026;	 // 0x1ff0 Reserved 2026.
	volatile uint32_t RSVD_2027;	 // 0x1ff4 Reserved 2027.
	volatile uint32_t RSVD_2028;	 // 0x1ff8 Reserved 2028.
	volatile uint32_t RSVD_2029;	 // 0x1ffc Reserved 2029.
	volatile uint32_t RSVD_2030;	 // 0x2000 Reserved 2030.
	volatile uint32_t RSVD_2031;	 // 0x2004 Reserved 2031.
	volatile uint32_t RSVD_2032;	 // 0x2008 Reserved 2032.
	volatile uint32_t RSVD_2033;	 // 0x200c Reserved 2033.
	volatile uint32_t RSVD_2034;	 // 0x2010 Reserved 2034.
	volatile uint32_t RSVD_2035;	 // 0x2014 Reserved 2035.
	volatile uint32_t RSVD_2036;	 // 0x2018 Reserved 2036.
	volatile uint32_t RSVD_2037;	 // 0x201c Reserved 2037.
	volatile uint32_t RSVD_2038;	 // 0x2020 Reserved 2038.
	volatile uint32_t RSVD_2039;	 // 0x2024 Reserved 2039.
	volatile uint32_t RSVD_2040;	 // 0x2028 Reserved 2040.
	volatile uint32_t RSVD_2041;	 // 0x202c Reserved 2041.
	volatile uint32_t RSVD_2042;	 // 0x2030 Reserved 2042.
	volatile uint32_t RSVD_2043;	 // 0x2034 Reserved 2043.
	volatile uint32_t RSVD_2044;	 // 0x2038 Reserved 2044.
	volatile uint32_t RSVD_2045;	 // 0x203c Reserved 2045.
	volatile uint32_t RSVD_2046;	 // 0x2040 Reserved 2046.
	volatile uint32_t RSVD_2047;	 // 0x2044 Reserved 2047.
	volatile uint32_t RSVD_2048;	 // 0x2048 Reserved 2048.
	volatile uint32_t RSVD_2049;	 // 0x204c Reserved 2049.
	volatile uint32_t RSVD_2050;	 // 0x2050 Reserved 2050.
	volatile uint32_t RSVD_2051;	 // 0x2054 Reserved 2051.
	volatile uint32_t RSVD_2052;	 // 0x2058 Reserved 2052.
	volatile uint32_t RSVD_2053;	 // 0x205c Reserved 2053.
	volatile uint32_t RSVD_2054;	 // 0x2060 Reserved 2054.
	volatile uint32_t RSVD_2055;	 // 0x2064 Reserved 2055.
	volatile uint32_t RSVD_2056;	 // 0x2068 Reserved 2056.
	volatile uint32_t RSVD_2057;	 // 0x206c Reserved 2057.
	volatile uint32_t RSVD_2058;	 // 0x2070 Reserved 2058.
	volatile uint32_t RSVD_2059;	 // 0x2074 Reserved 2059.
	volatile uint32_t RSVD_2060;	 // 0x2078 Reserved 2060.
	volatile uint32_t RSVD_2061;	 // 0x207c Reserved 2061.
	volatile uint32_t RSVD_2062;	 // 0x2080 Reserved 2062.
	volatile uint32_t RSVD_2063;	 // 0x2084 Reserved 2063.
	volatile uint32_t RSVD_2064;	 // 0x2088 Reserved 2064.
	volatile uint32_t RSVD_2065;	 // 0x208c Reserved 2065.
	volatile uint32_t RSVD_2066;	 // 0x2090 Reserved 2066.
	volatile uint32_t RSVD_2067;	 // 0x2094 Reserved 2067.
	volatile uint32_t RSVD_2068;	 // 0x2098 Reserved 2068.
	volatile uint32_t RSVD_2069;	 // 0x209c Reserved 2069.
	volatile uint32_t RSVD_2070;	 // 0x20a0 Reserved 2070.
	volatile uint32_t RSVD_2071;	 // 0x20a4 Reserved 2071.
	volatile uint32_t RSVD_2072;	 // 0x20a8 Reserved 2072.
	volatile uint32_t RSVD_2073;	 // 0x20ac Reserved 2073.
	volatile uint32_t RSVD_2074;	 // 0x20b0 Reserved 2074.
	volatile uint32_t RSVD_2075;	 // 0x20b4 Reserved 2075.
	volatile uint32_t RSVD_2076;	 // 0x20b8 Reserved 2076.
	volatile uint32_t RSVD_2077;	 // 0x20bc Reserved 2077.
	volatile uint32_t RSVD_2078;	 // 0x20c0 Reserved 2078.
	volatile uint32_t RSVD_2079;	 // 0x20c4 Reserved 2079.
	volatile uint32_t RSVD_2080;	 // 0x20c8 Reserved 2080.
	volatile uint32_t RSVD_2081;	 // 0x20cc Reserved 2081.
	volatile uint32_t RSVD_2082;	 // 0x20d0 Reserved 2082.
	volatile uint32_t RSVD_2083;	 // 0x20d4 Reserved 2083.
	volatile uint32_t RSVD_2084;	 // 0x20d8 Reserved 2084.
	volatile uint32_t RSVD_2085;	 // 0x20dc Reserved 2085.
	volatile uint32_t RSVD_2086;	 // 0x20e0 Reserved 2086.
	volatile uint32_t RSVD_2087;	 // 0x20e4 Reserved 2087.
	volatile uint32_t RSVD_2088;	 // 0x20e8 Reserved 2088.
	volatile uint32_t RSVD_2089;	 // 0x20ec Reserved 2089.
	volatile uint32_t RSVD_2090;	 // 0x20f0 Reserved 2090.
	volatile uint32_t RSVD_2091;	 // 0x20f4 Reserved 2091.
	volatile uint32_t RSVD_2092;	 // 0x20f8 Reserved 2092.
	volatile uint32_t RSVD_2093;	 // 0x20fc Reserved 2093.
	volatile uint32_t RSVD_2094;	 // 0x2100 Reserved 2094.
	volatile uint32_t RSVD_2095;	 // 0x2104 Reserved 2095.
	volatile uint32_t RSVD_2096;	 // 0x2108 Reserved 2096.
	volatile uint32_t RSVD_2097;	 // 0x210c Reserved 2097.
	volatile uint32_t RSVD_2098;	 // 0x2110 Reserved 2098.
	volatile uint32_t RSVD_2099;	 // 0x2114 Reserved 2099.
	volatile uint32_t RSVD_2100;	 // 0x2118 Reserved 2100.
	volatile uint32_t RSVD_2101;	 // 0x211c Reserved 2101.
	volatile uint32_t RSVD_2102;	 // 0x2120 Reserved 2102.
	volatile uint32_t RSVD_2103;	 // 0x2124 Reserved 2103.
	volatile uint32_t RSVD_2104;	 // 0x2128 Reserved 2104.
	volatile uint32_t RSVD_2105;	 // 0x212c Reserved 2105.
	volatile uint32_t RSVD_2106;	 // 0x2130 Reserved 2106.
	volatile uint32_t RSVD_2107;	 // 0x2134 Reserved 2107.
	volatile uint32_t RSVD_2108;	 // 0x2138 Reserved 2108.
	volatile uint32_t RSVD_2109;	 // 0x213c Reserved 2109.
	volatile uint32_t RSVD_2110;	 // 0x2140 Reserved 2110.
	volatile uint32_t RSVD_2111;	 // 0x2144 Reserved 2111.
	volatile uint32_t RSVD_2112;	 // 0x2148 Reserved 2112.
	volatile uint32_t RSVD_2113;	 // 0x214c Reserved 2113.
	volatile uint32_t RSVD_2114;	 // 0x2150 Reserved 2114.
	volatile uint32_t RSVD_2115;	 // 0x2154 Reserved 2115.
	volatile uint32_t RSVD_2116;	 // 0x2158 Reserved 2116.
	volatile uint32_t RSVD_2117;	 // 0x215c Reserved 2117.
	volatile uint32_t RSVD_2118;	 // 0x2160 Reserved 2118.
	volatile uint32_t RSVD_2119;	 // 0x2164 Reserved 2119.
	volatile uint32_t RSVD_2120;	 // 0x2168 Reserved 2120.
	volatile uint32_t RSVD_2121;	 // 0x216c Reserved 2121.
	volatile uint32_t RSVD_2122;	 // 0x2170 Reserved 2122.
	volatile uint32_t RSVD_2123;	 // 0x2174 Reserved 2123.
	volatile uint32_t RSVD_2124;	 // 0x2178 Reserved 2124.
	volatile uint32_t RSVD_2125;	 // 0x217c Reserved 2125.
	volatile uint32_t RSVD_2126;	 // 0x2180 Reserved 2126.
	volatile uint32_t RSVD_2127;	 // 0x2184 Reserved 2127.
	volatile uint32_t RSVD_2128;	 // 0x2188 Reserved 2128.
	volatile uint32_t RSVD_2129;	 // 0x218c Reserved 2129.
	volatile uint32_t RSVD_2130;	 // 0x2190 Reserved 2130.
	volatile uint32_t RSVD_2131;	 // 0x2194 Reserved 2131.
	volatile uint32_t RSVD_2132;	 // 0x2198 Reserved 2132.
	volatile uint32_t RSVD_2133;	 // 0x219c Reserved 2133.
	volatile uint32_t RSVD_2134;	 // 0x21a0 Reserved 2134.
	volatile uint32_t RSVD_2135;	 // 0x21a4 Reserved 2135.
	volatile uint32_t RSVD_2136;	 // 0x21a8 Reserved 2136.
	volatile uint32_t RSVD_2137;	 // 0x21ac Reserved 2137.
	volatile uint32_t RSVD_2138;	 // 0x21b0 Reserved 2138.
	volatile uint32_t RSVD_2139;	 // 0x21b4 Reserved 2139.
	volatile uint32_t RSVD_2140;	 // 0x21b8 Reserved 2140.
	volatile uint32_t RSVD_2141;	 // 0x21bc Reserved 2141.
	volatile uint32_t RSVD_2142;	 // 0x21c0 Reserved 2142.
	volatile uint32_t RSVD_2143;	 // 0x21c4 Reserved 2143.
	volatile uint32_t RSVD_2144;	 // 0x21c8 Reserved 2144.
	volatile uint32_t RSVD_2145;	 // 0x21cc Reserved 2145.
	volatile uint32_t RSVD_2146;	 // 0x21d0 Reserved 2146.
	volatile uint32_t RSVD_2147;	 // 0x21d4 Reserved 2147.
	volatile uint32_t RSVD_2148;	 // 0x21d8 Reserved 2148.
	volatile uint32_t RSVD_2149;	 // 0x21dc Reserved 2149.
	volatile uint32_t RSVD_2150;	 // 0x21e0 Reserved 2150.
	volatile uint32_t RSVD_2151;	 // 0x21e4 Reserved 2151.
	volatile uint32_t RSVD_2152;	 // 0x21e8 Reserved 2152.
	volatile uint32_t RSVD_2153;	 // 0x21ec Reserved 2153.
	volatile uint32_t RSVD_2154;	 // 0x21f0 Reserved 2154.
	volatile uint32_t RSVD_2155;	 // 0x21f4 Reserved 2155.
	volatile uint32_t RSVD_2156;	 // 0x21f8 Reserved 2156.
	volatile uint32_t RSVD_2157;	 // 0x21fc Reserved 2157.
	volatile uint32_t RSVD_2158;	 // 0x2200 Reserved 2158.
	volatile uint32_t RSVD_2159;	 // 0x2204 Reserved 2159.
	volatile uint32_t RSVD_2160;	 // 0x2208 Reserved 2160.
	volatile uint32_t RSVD_2161;	 // 0x220c Reserved 2161.
	volatile uint32_t RSVD_2162;	 // 0x2210 Reserved 2162.
	volatile uint32_t RSVD_2163;	 // 0x2214 Reserved 2163.
	volatile uint32_t RSVD_2164;	 // 0x2218 Reserved 2164.
	volatile uint32_t RSVD_2165;	 // 0x221c Reserved 2165.
	volatile uint32_t RSVD_2166;	 // 0x2220 Reserved 2166.
	volatile uint32_t RSVD_2167;	 // 0x2224 Reserved 2167.
	volatile uint32_t RSVD_2168;	 // 0x2228 Reserved 2168.
	volatile uint32_t RSVD_2169;	 // 0x222c Reserved 2169.
	volatile uint32_t RSVD_2170;	 // 0x2230 Reserved 2170.
	volatile uint32_t RSVD_2171;	 // 0x2234 Reserved 2171.
	volatile uint32_t RSVD_2172;	 // 0x2238 Reserved 2172.
	volatile uint32_t RSVD_2173;	 // 0x223c Reserved 2173.
	volatile uint32_t RSVD_2174;	 // 0x2240 Reserved 2174.
	volatile uint32_t RSVD_2175;	 // 0x2244 Reserved 2175.
	volatile uint32_t RSVD_2176;	 // 0x2248 Reserved 2176.
	volatile uint32_t RSVD_2177;	 // 0x224c Reserved 2177.
	volatile uint32_t RSVD_2178;	 // 0x2250 Reserved 2178.
	volatile uint32_t RSVD_2179;	 // 0x2254 Reserved 2179.
	volatile uint32_t RSVD_2180;	 // 0x2258 Reserved 2180.
	volatile uint32_t RSVD_2181;	 // 0x225c Reserved 2181.
	volatile uint32_t RSVD_2182;	 // 0x2260 Reserved 2182.
	volatile uint32_t RSVD_2183;	 // 0x2264 Reserved 2183.
	volatile uint32_t RSVD_2184;	 // 0x2268 Reserved 2184.
	volatile uint32_t RSVD_2185;	 // 0x226c Reserved 2185.
	volatile uint32_t RSVD_2186;	 // 0x2270 Reserved 2186.
	volatile uint32_t RSVD_2187;	 // 0x2274 Reserved 2187.
	volatile uint32_t RSVD_2188;	 // 0x2278 Reserved 2188.
	volatile uint32_t RSVD_2189;	 // 0x227c Reserved 2189.
	volatile uint32_t RSVD_2190;	 // 0x2280 Reserved 2190.
	volatile uint32_t RSVD_2191;	 // 0x2284 Reserved 2191.
	volatile uint32_t RSVD_2192;	 // 0x2288 Reserved 2192.
	volatile uint32_t RSVD_2193;	 // 0x228c Reserved 2193.
	volatile uint32_t RSVD_2194;	 // 0x2290 Reserved 2194.
	volatile uint32_t RSVD_2195;	 // 0x2294 Reserved 2195.
	volatile uint32_t RSVD_2196;	 // 0x2298 Reserved 2196.
	volatile uint32_t RSVD_2197;	 // 0x229c Reserved 2197.
	volatile uint32_t RSVD_2198;	 // 0x22a0 Reserved 2198.
	volatile uint32_t RSVD_2199;	 // 0x22a4 Reserved 2199.
	volatile uint32_t RSVD_2200;	 // 0x22a8 Reserved 2200.
	volatile uint32_t RSVD_2201;	 // 0x22ac Reserved 2201.
	volatile uint32_t RSVD_2202;	 // 0x22b0 Reserved 2202.
	volatile uint32_t RSVD_2203;	 // 0x22b4 Reserved 2203.
	volatile uint32_t RSVD_2204;	 // 0x22b8 Reserved 2204.
	volatile uint32_t RSVD_2205;	 // 0x22bc Reserved 2205.
	volatile uint32_t RSVD_2206;	 // 0x22c0 Reserved 2206.
	volatile uint32_t RSVD_2207;	 // 0x22c4 Reserved 2207.
	volatile uint32_t RSVD_2208;	 // 0x22c8 Reserved 2208.
	volatile uint32_t RSVD_2209;	 // 0x22cc Reserved 2209.
	volatile uint32_t RSVD_2210;	 // 0x22d0 Reserved 2210.
	volatile uint32_t RSVD_2211;	 // 0x22d4 Reserved 2211.
	volatile uint32_t RSVD_2212;	 // 0x22d8 Reserved 2212.
	volatile uint32_t RSVD_2213;	 // 0x22dc Reserved 2213.
	volatile uint32_t RSVD_2214;	 // 0x22e0 Reserved 2214.
	volatile uint32_t RSVD_2215;	 // 0x22e4 Reserved 2215.
	volatile uint32_t RSVD_2216;	 // 0x22e8 Reserved 2216.
	volatile uint32_t RSVD_2217;	 // 0x22ec Reserved 2217.
	volatile uint32_t RSVD_2218;	 // 0x22f0 Reserved 2218.
	volatile uint32_t RSVD_2219;	 // 0x22f4 Reserved 2219.
	volatile uint32_t RSVD_2220;	 // 0x22f8 Reserved 2220.
	volatile uint32_t RSVD_2221;	 // 0x22fc Reserved 2221.
	volatile uint32_t RSVD_2222;	 // 0x2300 Reserved 2222.
	volatile uint32_t RSVD_2223;	 // 0x2304 Reserved 2223.
	volatile uint32_t RSVD_2224;	 // 0x2308 Reserved 2224.
	volatile uint32_t RSVD_2225;	 // 0x230c Reserved 2225.
	volatile uint32_t RSVD_2226;	 // 0x2310 Reserved 2226.
	volatile uint32_t RSVD_2227;	 // 0x2314 Reserved 2227.
	volatile uint32_t RSVD_2228;	 // 0x2318 Reserved 2228.
	volatile uint32_t RSVD_2229;	 // 0x231c Reserved 2229.
	volatile uint32_t RSVD_2230;	 // 0x2320 Reserved 2230.
	volatile uint32_t RSVD_2231;	 // 0x2324 Reserved 2231.
	volatile uint32_t RSVD_2232;	 // 0x2328 Reserved 2232.
	volatile uint32_t RSVD_2233;	 // 0x232c Reserved 2233.
	volatile uint32_t RSVD_2234;	 // 0x2330 Reserved 2234.
	volatile uint32_t RSVD_2235;	 // 0x2334 Reserved 2235.
	volatile uint32_t RSVD_2236;	 // 0x2338 Reserved 2236.
	volatile uint32_t RSVD_2237;	 // 0x233c Reserved 2237.
	volatile uint32_t RSVD_2238;	 // 0x2340 Reserved 2238.
	volatile uint32_t RSVD_2239;	 // 0x2344 Reserved 2239.
	volatile uint32_t RSVD_2240;	 // 0x2348 Reserved 2240.
	volatile uint32_t RSVD_2241;	 // 0x234c Reserved 2241.
	volatile uint32_t RSVD_2242;	 // 0x2350 Reserved 2242.
	volatile uint32_t RSVD_2243;	 // 0x2354 Reserved 2243.
	volatile uint32_t RSVD_2244;	 // 0x2358 Reserved 2244.
	volatile uint32_t RSVD_2245;	 // 0x235c Reserved 2245.
	volatile uint32_t RSVD_2246;	 // 0x2360 Reserved 2246.
	volatile uint32_t RSVD_2247;	 // 0x2364 Reserved 2247.
	volatile uint32_t RSVD_2248;	 // 0x2368 Reserved 2248.
	volatile uint32_t RSVD_2249;	 // 0x236c Reserved 2249.
	volatile uint32_t RSVD_2250;	 // 0x2370 Reserved 2250.
	volatile uint32_t RSVD_2251;	 // 0x2374 Reserved 2251.
	volatile uint32_t RSVD_2252;	 // 0x2378 Reserved 2252.
	volatile uint32_t RSVD_2253;	 // 0x237c Reserved 2253.
	volatile uint32_t RSVD_2254;	 // 0x2380 Reserved 2254.
	volatile uint32_t RSVD_2255;	 // 0x2384 Reserved 2255.
	volatile uint32_t RSVD_2256;	 // 0x2388 Reserved 2256.
	volatile uint32_t RSVD_2257;	 // 0x238c Reserved 2257.
	volatile uint32_t RSVD_2258;	 // 0x2390 Reserved 2258.
	volatile uint32_t RSVD_2259;	 // 0x2394 Reserved 2259.
	volatile uint32_t RSVD_2260;	 // 0x2398 Reserved 2260.
	volatile uint32_t RSVD_2261;	 // 0x239c Reserved 2261.
	volatile uint32_t RSVD_2262;	 // 0x23a0 Reserved 2262.
	volatile uint32_t RSVD_2263;	 // 0x23a4 Reserved 2263.
	volatile uint32_t RSVD_2264;	 // 0x23a8 Reserved 2264.
	volatile uint32_t RSVD_2265;	 // 0x23ac Reserved 2265.
	volatile uint32_t RSVD_2266;	 // 0x23b0 Reserved 2266.
	volatile uint32_t RSVD_2267;	 // 0x23b4 Reserved 2267.
	volatile uint32_t RSVD_2268;	 // 0x23b8 Reserved 2268.
	volatile uint32_t RSVD_2269;	 // 0x23bc Reserved 2269.
	volatile uint32_t RSVD_2270;	 // 0x23c0 Reserved 2270.
	volatile uint32_t RSVD_2271;	 // 0x23c4 Reserved 2271.
	volatile uint32_t RSVD_2272;	 // 0x23c8 Reserved 2272.
	volatile uint32_t RSVD_2273;	 // 0x23cc Reserved 2273.
	volatile uint32_t RSVD_2274;	 // 0x23d0 Reserved 2274.
	volatile uint32_t RSVD_2275;	 // 0x23d4 Reserved 2275.
	volatile uint32_t RSVD_2276;	 // 0x23d8 Reserved 2276.
	volatile uint32_t RSVD_2277;	 // 0x23dc Reserved 2277.
	volatile uint32_t RSVD_2278;	 // 0x23e0 Reserved 2278.
	volatile uint32_t RSVD_2279;	 // 0x23e4 Reserved 2279.
	volatile uint32_t RSVD_2280;	 // 0x23e8 Reserved 2280.
	volatile uint32_t RSVD_2281;	 // 0x23ec Reserved 2281.
	volatile uint32_t RSVD_2282;	 // 0x23f0 Reserved 2282.
	volatile uint32_t RSVD_2283;	 // 0x23f4 Reserved 2283.
	volatile uint32_t RSVD_2284;	 // 0x23f8 Reserved 2284.
	volatile uint32_t RSVD_2285;	 // 0x23fc Reserved 2285.
	volatile uint32_t RSVD_2286;	 // 0x2400 Reserved 2286.
	volatile uint32_t RSVD_2287;	 // 0x2404 Reserved 2287.
	volatile uint32_t RSVD_2288;	 // 0x2408 Reserved 2288.
	volatile uint32_t RSVD_2289;	 // 0x240c Reserved 2289.
	volatile uint32_t RSVD_2290;	 // 0x2410 Reserved 2290.
	volatile uint32_t RSVD_2291;	 // 0x2414 Reserved 2291.
	volatile uint32_t RSVD_2292;	 // 0x2418 Reserved 2292.
	volatile uint32_t RSVD_2293;	 // 0x241c Reserved 2293.
	volatile uint32_t RSVD_2294;	 // 0x2420 Reserved 2294.
	volatile uint32_t RSVD_2295;	 // 0x2424 Reserved 2295.
	volatile uint32_t RSVD_2296;	 // 0x2428 Reserved 2296.
	volatile uint32_t RSVD_2297;	 // 0x242c Reserved 2297.
	volatile uint32_t RSVD_2298;	 // 0x2430 Reserved 2298.
	volatile uint32_t RSVD_2299;	 // 0x2434 Reserved 2299.
	volatile uint32_t RSVD_2300;	 // 0x2438 Reserved 2300.
	volatile uint32_t RSVD_2301;	 // 0x243c Reserved 2301.
	volatile uint32_t RSVD_2302;	 // 0x2440 Reserved 2302.
	volatile uint32_t RSVD_2303;	 // 0x2444 Reserved 2303.
	volatile uint32_t RSVD_2304;	 // 0x2448 Reserved 2304.
	volatile uint32_t RSVD_2305;	 // 0x244c Reserved 2305.
	volatile uint32_t RSVD_2306;	 // 0x2450 Reserved 2306.
	volatile uint32_t RSVD_2307;	 // 0x2454 Reserved 2307.
	volatile uint32_t RSVD_2308;	 // 0x2458 Reserved 2308.
	volatile uint32_t RSVD_2309;	 // 0x245c Reserved 2309.
	volatile uint32_t RSVD_2310;	 // 0x2460 Reserved 2310.
	volatile uint32_t RSVD_2311;	 // 0x2464 Reserved 2311.
	volatile uint32_t RSVD_2312;	 // 0x2468 Reserved 2312.
	volatile uint32_t RSVD_2313;	 // 0x246c Reserved 2313.
	volatile uint32_t RSVD_2314;	 // 0x2470 Reserved 2314.
	volatile uint32_t RSVD_2315;	 // 0x2474 Reserved 2315.
	volatile uint32_t RSVD_2316;	 // 0x2478 Reserved 2316.
	volatile uint32_t RSVD_2317;	 // 0x247c Reserved 2317.
	volatile uint32_t RSVD_2318;	 // 0x2480 Reserved 2318.
	volatile uint32_t RSVD_2319;	 // 0x2484 Reserved 2319.
	volatile uint32_t RSVD_2320;	 // 0x2488 Reserved 2320.
	volatile uint32_t RSVD_2321;	 // 0x248c Reserved 2321.
	volatile uint32_t RSVD_2322;	 // 0x2490 Reserved 2322.
	volatile uint32_t RSVD_2323;	 // 0x2494 Reserved 2323.
	volatile uint32_t RSVD_2324;	 // 0x2498 Reserved 2324.
	volatile uint32_t RSVD_2325;	 // 0x249c Reserved 2325.
	volatile uint32_t RSVD_2326;	 // 0x24a0 Reserved 2326.
	volatile uint32_t RSVD_2327;	 // 0x24a4 Reserved 2327.
	volatile uint32_t RSVD_2328;	 // 0x24a8 Reserved 2328.
	volatile uint32_t RSVD_2329;	 // 0x24ac Reserved 2329.
	volatile uint32_t RSVD_2330;	 // 0x24b0 Reserved 2330.
	volatile uint32_t RSVD_2331;	 // 0x24b4 Reserved 2331.
	volatile uint32_t RSVD_2332;	 // 0x24b8 Reserved 2332.
	volatile uint32_t RSVD_2333;	 // 0x24bc Reserved 2333.
	volatile uint32_t RSVD_2334;	 // 0x24c0 Reserved 2334.
	volatile uint32_t RSVD_2335;	 // 0x24c4 Reserved 2335.
	volatile uint32_t RSVD_2336;	 // 0x24c8 Reserved 2336.
	volatile uint32_t RSVD_2337;	 // 0x24cc Reserved 2337.
	volatile uint32_t RSVD_2338;	 // 0x24d0 Reserved 2338.
	volatile uint32_t RSVD_2339;	 // 0x24d4 Reserved 2339.
	volatile uint32_t RSVD_2340;	 // 0x24d8 Reserved 2340.
	volatile uint32_t RSVD_2341;	 // 0x24dc Reserved 2341.
	volatile uint32_t RSVD_2342;	 // 0x24e0 Reserved 2342.
	volatile uint32_t RSVD_2343;	 // 0x24e4 Reserved 2343.
	volatile uint32_t RSVD_2344;	 // 0x24e8 Reserved 2344.
	volatile uint32_t RSVD_2345;	 // 0x24ec Reserved 2345.
	volatile uint32_t RSVD_2346;	 // 0x24f0 Reserved 2346.
	volatile uint32_t RSVD_2347;	 // 0x24f4 Reserved 2347.
	volatile uint32_t RSVD_2348;	 // 0x24f8 Reserved 2348.
	volatile uint32_t RSVD_2349;	 // 0x24fc Reserved 2349.
	volatile uint32_t RSVD_2350;	 // 0x2500 Reserved 2350.
	volatile uint32_t RSVD_2351;	 // 0x2504 Reserved 2351.
	volatile uint32_t RSVD_2352;	 // 0x2508 Reserved 2352.
	volatile uint32_t RSVD_2353;	 // 0x250c Reserved 2353.
	volatile uint32_t RSVD_2354;	 // 0x2510 Reserved 2354.
	volatile uint32_t RSVD_2355;	 // 0x2514 Reserved 2355.
	volatile uint32_t RSVD_2356;	 // 0x2518 Reserved 2356.
	volatile uint32_t RSVD_2357;	 // 0x251c Reserved 2357.
	volatile uint32_t RSVD_2358;	 // 0x2520 Reserved 2358.
	volatile uint32_t RSVD_2359;	 // 0x2524 Reserved 2359.
	volatile uint32_t RSVD_2360;	 // 0x2528 Reserved 2360.
	volatile uint32_t RSVD_2361;	 // 0x252c Reserved 2361.
	volatile uint32_t RSVD_2362;	 // 0x2530 Reserved 2362.
	volatile uint32_t RSVD_2363;	 // 0x2534 Reserved 2363.
	volatile uint32_t RSVD_2364;	 // 0x2538 Reserved 2364.
	volatile uint32_t RSVD_2365;	 // 0x253c Reserved 2365.
	volatile uint32_t RSVD_2366;	 // 0x2540 Reserved 2366.
	volatile uint32_t RSVD_2367;	 // 0x2544 Reserved 2367.
	volatile uint32_t RSVD_2368;	 // 0x2548 Reserved 2368.
	volatile uint32_t RSVD_2369;	 // 0x254c Reserved 2369.
	volatile uint32_t RSVD_2370;	 // 0x2550 Reserved 2370.
	volatile uint32_t RSVD_2371;	 // 0x2554 Reserved 2371.
	volatile uint32_t RSVD_2372;	 // 0x2558 Reserved 2372.
	volatile uint32_t RSVD_2373;	 // 0x255c Reserved 2373.
	volatile uint32_t RSVD_2374;	 // 0x2560 Reserved 2374.
	volatile uint32_t RSVD_2375;	 // 0x2564 Reserved 2375.
	volatile uint32_t RSVD_2376;	 // 0x2568 Reserved 2376.
	volatile uint32_t RSVD_2377;	 // 0x256c Reserved 2377.
	volatile uint32_t RSVD_2378;	 // 0x2570 Reserved 2378.
	volatile uint32_t RSVD_2379;	 // 0x2574 Reserved 2379.
	volatile uint32_t RSVD_2380;	 // 0x2578 Reserved 2380.
	volatile uint32_t RSVD_2381;	 // 0x257c Reserved 2381.
	volatile uint32_t RSVD_2382;	 // 0x2580 Reserved 2382.
	volatile uint32_t RSVD_2383;	 // 0x2584 Reserved 2383.
	volatile uint32_t RSVD_2384;	 // 0x2588 Reserved 2384.
	volatile uint32_t RSVD_2385;	 // 0x258c Reserved 2385.
	volatile uint32_t RSVD_2386;	 // 0x2590 Reserved 2386.
	volatile uint32_t RSVD_2387;	 // 0x2594 Reserved 2387.
	volatile uint32_t RSVD_2388;	 // 0x2598 Reserved 2388.
	volatile uint32_t RSVD_2389;	 // 0x259c Reserved 2389.
	volatile uint32_t RSVD_2390;	 // 0x25a0 Reserved 2390.
	volatile uint32_t RSVD_2391;	 // 0x25a4 Reserved 2391.
	volatile uint32_t RSVD_2392;	 // 0x25a8 Reserved 2392.
	volatile uint32_t RSVD_2393;	 // 0x25ac Reserved 2393.
	volatile uint32_t RSVD_2394;	 // 0x25b0 Reserved 2394.
	volatile uint32_t RSVD_2395;	 // 0x25b4 Reserved 2395.
	volatile uint32_t RSVD_2396;	 // 0x25b8 Reserved 2396.
	volatile uint32_t RSVD_2397;	 // 0x25bc Reserved 2397.
	volatile uint32_t RSVD_2398;	 // 0x25c0 Reserved 2398.
	volatile uint32_t RSVD_2399;	 // 0x25c4 Reserved 2399.
	volatile uint32_t RSVD_2400;	 // 0x25c8 Reserved 2400.
	volatile uint32_t RSVD_2401;	 // 0x25cc Reserved 2401.
	volatile uint32_t RSVD_2402;	 // 0x25d0 Reserved 2402.
	volatile uint32_t RSVD_2403;	 // 0x25d4 Reserved 2403.
	volatile uint32_t RSVD_2404;	 // 0x25d8 Reserved 2404.
	volatile uint32_t RSVD_2405;	 // 0x25dc Reserved 2405.
	volatile uint32_t RSVD_2406;	 // 0x25e0 Reserved 2406.
	volatile uint32_t RSVD_2407;	 // 0x25e4 Reserved 2407.
	volatile uint32_t RSVD_2408;	 // 0x25e8 Reserved 2408.
	volatile uint32_t RSVD_2409;	 // 0x25ec Reserved 2409.
	volatile uint32_t RSVD_2410;	 // 0x25f0 Reserved 2410.
	volatile uint32_t RSVD_2411;	 // 0x25f4 Reserved 2411.
	volatile uint32_t RSVD_2412;	 // 0x25f8 Reserved 2412.
	volatile uint32_t RSVD_2413;	 // 0x25fc Reserved 2413.
	volatile uint32_t RSVD_2414;	 // 0x2600 Reserved 2414.
	volatile uint32_t RSVD_2415;	 // 0x2604 Reserved 2415.
	volatile uint32_t RSVD_2416;	 // 0x2608 Reserved 2416.
	volatile uint32_t RSVD_2417;	 // 0x260c Reserved 2417.
	volatile uint32_t RSVD_2418;	 // 0x2610 Reserved 2418.
	volatile uint32_t RSVD_2419;	 // 0x2614 Reserved 2419.
	volatile uint32_t RSVD_2420;	 // 0x2618 Reserved 2420.
	volatile uint32_t RSVD_2421;	 // 0x261c Reserved 2421.
	volatile uint32_t RSVD_2422;	 // 0x2620 Reserved 2422.
	volatile uint32_t RSVD_2423;	 // 0x2624 Reserved 2423.
	volatile uint32_t RSVD_2424;	 // 0x2628 Reserved 2424.
	volatile uint32_t RSVD_2425;	 // 0x262c Reserved 2425.
	volatile uint32_t RSVD_2426;	 // 0x2630 Reserved 2426.
	volatile uint32_t RSVD_2427;	 // 0x2634 Reserved 2427.
	volatile uint32_t RSVD_2428;	 // 0x2638 Reserved 2428.
	volatile uint32_t RSVD_2429;	 // 0x263c Reserved 2429.
	volatile uint32_t RSVD_2430;	 // 0x2640 Reserved 2430.
	volatile uint32_t RSVD_2431;	 // 0x2644 Reserved 2431.
	volatile uint32_t RSVD_2432;	 // 0x2648 Reserved 2432.
	volatile uint32_t RSVD_2433;	 // 0x264c Reserved 2433.
	volatile uint32_t RSVD_2434;	 // 0x2650 Reserved 2434.
	volatile uint32_t RSVD_2435;	 // 0x2654 Reserved 2435.
	volatile uint32_t RSVD_2436;	 // 0x2658 Reserved 2436.
	volatile uint32_t RSVD_2437;	 // 0x265c Reserved 2437.
	volatile uint32_t RSVD_2438;	 // 0x2660 Reserved 2438.
	volatile uint32_t RSVD_2439;	 // 0x2664 Reserved 2439.
	volatile uint32_t RSVD_2440;	 // 0x2668 Reserved 2440.
	volatile uint32_t RSVD_2441;	 // 0x266c Reserved 2441.
	volatile uint32_t RSVD_2442;	 // 0x2670 Reserved 2442.
	volatile uint32_t RSVD_2443;	 // 0x2674 Reserved 2443.
	volatile uint32_t RSVD_2444;	 // 0x2678 Reserved 2444.
	volatile uint32_t RSVD_2445;	 // 0x267c Reserved 2445.
	volatile uint32_t RSVD_2446;	 // 0x2680 Reserved 2446.
	volatile uint32_t RSVD_2447;	 // 0x2684 Reserved 2447.
	volatile uint32_t RSVD_2448;	 // 0x2688 Reserved 2448.
	volatile uint32_t RSVD_2449;	 // 0x268c Reserved 2449.
	volatile uint32_t RSVD_2450;	 // 0x2690 Reserved 2450.
	volatile uint32_t RSVD_2451;	 // 0x2694 Reserved 2451.
	volatile uint32_t RSVD_2452;	 // 0x2698 Reserved 2452.
	volatile uint32_t RSVD_2453;	 // 0x269c Reserved 2453.
	volatile uint32_t RSVD_2454;	 // 0x26a0 Reserved 2454.
	volatile uint32_t RSVD_2455;	 // 0x26a4 Reserved 2455.
	volatile uint32_t RSVD_2456;	 // 0x26a8 Reserved 2456.
	volatile uint32_t RSVD_2457;	 // 0x26ac Reserved 2457.
	volatile uint32_t RSVD_2458;	 // 0x26b0 Reserved 2458.
	volatile uint32_t RSVD_2459;	 // 0x26b4 Reserved 2459.
	volatile uint32_t RSVD_2460;	 // 0x26b8 Reserved 2460.
	volatile uint32_t RSVD_2461;	 // 0x26bc Reserved 2461.
	volatile uint32_t RSVD_2462;	 // 0x26c0 Reserved 2462.
	volatile uint32_t RSVD_2463;	 // 0x26c4 Reserved 2463.
	volatile uint32_t RSVD_2464;	 // 0x26c8 Reserved 2464.
	volatile uint32_t RSVD_2465;	 // 0x26cc Reserved 2465.
	volatile uint32_t RSVD_2466;	 // 0x26d0 Reserved 2466.
	volatile uint32_t RSVD_2467;	 // 0x26d4 Reserved 2467.
	volatile uint32_t RSVD_2468;	 // 0x26d8 Reserved 2468.
	volatile uint32_t RSVD_2469;	 // 0x26dc Reserved 2469.
	volatile uint32_t RSVD_2470;	 // 0x26e0 Reserved 2470.
	volatile uint32_t RSVD_2471;	 // 0x26e4 Reserved 2471.
	volatile uint32_t RSVD_2472;	 // 0x26e8 Reserved 2472.
	volatile uint32_t RSVD_2473;	 // 0x26ec Reserved 2473.
	volatile uint32_t RSVD_2474;	 // 0x26f0 Reserved 2474.
	volatile uint32_t RSVD_2475;	 // 0x26f4 Reserved 2475.
	volatile uint32_t RSVD_2476;	 // 0x26f8 Reserved 2476.
	volatile uint32_t RSVD_2477;	 // 0x26fc Reserved 2477.
	volatile uint32_t RSVD_2478;	 // 0x2700 Reserved 2478.
	volatile uint32_t RSVD_2479;	 // 0x2704 Reserved 2479.
	volatile uint32_t RSVD_2480;	 // 0x2708 Reserved 2480.
	volatile uint32_t RSVD_2481;	 // 0x270c Reserved 2481.
	volatile uint32_t RSVD_2482;	 // 0x2710 Reserved 2482.
	volatile uint32_t RSVD_2483;	 // 0x2714 Reserved 2483.
	volatile uint32_t RSVD_2484;	 // 0x2718 Reserved 2484.
	volatile uint32_t RSVD_2485;	 // 0x271c Reserved 2485.
	volatile uint32_t RSVD_2486;	 // 0x2720 Reserved 2486.
	volatile uint32_t RSVD_2487;	 // 0x2724 Reserved 2487.
	volatile uint32_t RSVD_2488;	 // 0x2728 Reserved 2488.
	volatile uint32_t RSVD_2489;	 // 0x272c Reserved 2489.
	volatile uint32_t RSVD_2490;	 // 0x2730 Reserved 2490.
	volatile uint32_t RSVD_2491;	 // 0x2734 Reserved 2491.
	volatile uint32_t RSVD_2492;	 // 0x2738 Reserved 2492.
	volatile uint32_t RSVD_2493;	 // 0x273c Reserved 2493.
	volatile uint32_t RSVD_2494;	 // 0x2740 Reserved 2494.
	volatile uint32_t RSVD_2495;	 // 0x2744 Reserved 2495.
	volatile uint32_t RSVD_2496;	 // 0x2748 Reserved 2496.
	volatile uint32_t RSVD_2497;	 // 0x274c Reserved 2497.
	volatile uint32_t RSVD_2498;	 // 0x2750 Reserved 2498.
	volatile uint32_t RSVD_2499;	 // 0x2754 Reserved 2499.
	volatile uint32_t RSVD_2500;	 // 0x2758 Reserved 2500.
	volatile uint32_t RSVD_2501;	 // 0x275c Reserved 2501.
	volatile uint32_t RSVD_2502;	 // 0x2760 Reserved 2502.
	volatile uint32_t RSVD_2503;	 // 0x2764 Reserved 2503.
	volatile uint32_t RSVD_2504;	 // 0x2768 Reserved 2504.
	volatile uint32_t RSVD_2505;	 // 0x276c Reserved 2505.
	volatile uint32_t RSVD_2506;	 // 0x2770 Reserved 2506.
	volatile uint32_t RSVD_2507;	 // 0x2774 Reserved 2507.
	volatile uint32_t RSVD_2508;	 // 0x2778 Reserved 2508.
	volatile uint32_t RSVD_2509;	 // 0x277c Reserved 2509.
	volatile uint32_t RSVD_2510;	 // 0x2780 Reserved 2510.
	volatile uint32_t RSVD_2511;	 // 0x2784 Reserved 2511.
	volatile uint32_t RSVD_2512;	 // 0x2788 Reserved 2512.
	volatile uint32_t RSVD_2513;	 // 0x278c Reserved 2513.
	volatile uint32_t RSVD_2514;	 // 0x2790 Reserved 2514.
	volatile uint32_t RSVD_2515;	 // 0x2794 Reserved 2515.
	volatile uint32_t RSVD_2516;	 // 0x2798 Reserved 2516.
	volatile uint32_t RSVD_2517;	 // 0x279c Reserved 2517.
	volatile uint32_t RSVD_2518;	 // 0x27a0 Reserved 2518.
	volatile uint32_t RSVD_2519;	 // 0x27a4 Reserved 2519.
	volatile uint32_t RSVD_2520;	 // 0x27a8 Reserved 2520.
	volatile uint32_t RSVD_2521;	 // 0x27ac Reserved 2521.
	volatile uint32_t RSVD_2522;	 // 0x27b0 Reserved 2522.
	volatile uint32_t RSVD_2523;	 // 0x27b4 Reserved 2523.
	volatile uint32_t RSVD_2524;	 // 0x27b8 Reserved 2524.
	volatile uint32_t RSVD_2525;	 // 0x27bc Reserved 2525.
	volatile uint32_t RSVD_2526;	 // 0x27c0 Reserved 2526.
	volatile uint32_t RSVD_2527;	 // 0x27c4 Reserved 2527.
	volatile uint32_t RSVD_2528;	 // 0x27c8 Reserved 2528.
	volatile uint32_t RSVD_2529;	 // 0x27cc Reserved 2529.
	volatile uint32_t RSVD_2530;	 // 0x27d0 Reserved 2530.
	volatile uint32_t RSVD_2531;	 // 0x27d4 Reserved 2531.
	volatile uint32_t RSVD_2532;	 // 0x27d8 Reserved 2532.
	volatile uint32_t RSVD_2533;	 // 0x27dc Reserved 2533.
	volatile uint32_t RSVD_2534;	 // 0x27e0 Reserved 2534.
	volatile uint32_t RSVD_2535;	 // 0x27e4 Reserved 2535.
	volatile uint32_t RSVD_2536;	 // 0x27e8 Reserved 2536.
	volatile uint32_t RSVD_2537;	 // 0x27ec Reserved 2537.
	volatile uint32_t RSVD_2538;	 // 0x27f0 Reserved 2538.
	volatile uint32_t RSVD_2539;	 // 0x27f4 Reserved 2539.
	volatile uint32_t RSVD_2540;	 // 0x27f8 Reserved 2540.
	volatile uint32_t RSVD_2541;	 // 0x27fc Reserved 2541.
	volatile uint32_t RSVD_2542;	 // 0x2800 Reserved 2542.
	volatile uint32_t RSVD_2543;	 // 0x2804 Reserved 2543.
	volatile uint32_t RSVD_2544;	 // 0x2808 Reserved 2544.
	volatile uint32_t RSVD_2545;	 // 0x280c Reserved 2545.
	volatile uint32_t RSVD_2546;	 // 0x2810 Reserved 2546.
	volatile uint32_t RSVD_2547;	 // 0x2814 Reserved 2547.
	volatile uint32_t RSVD_2548;	 // 0x2818 Reserved 2548.
	volatile uint32_t RSVD_2549;	 // 0x281c Reserved 2549.
	volatile uint32_t RSVD_2550;	 // 0x2820 Reserved 2550.
	volatile uint32_t RSVD_2551;	 // 0x2824 Reserved 2551.
	volatile uint32_t RSVD_2552;	 // 0x2828 Reserved 2552.
	volatile uint32_t RSVD_2553;	 // 0x282c Reserved 2553.
	volatile uint32_t RSVD_2554;	 // 0x2830 Reserved 2554.
	volatile uint32_t RSVD_2555;	 // 0x2834 Reserved 2555.
	volatile uint32_t RSVD_2556;	 // 0x2838 Reserved 2556.
	volatile uint32_t RSVD_2557;	 // 0x283c Reserved 2557.
	volatile uint32_t RSVD_2558;	 // 0x2840 Reserved 2558.
	volatile uint32_t RSVD_2559;	 // 0x2844 Reserved 2559.
	volatile uint32_t RSVD_2560;	 // 0x2848 Reserved 2560.
	volatile uint32_t RSVD_2561;	 // 0x284c Reserved 2561.
	volatile uint32_t RSVD_2562;	 // 0x2850 Reserved 2562.
	volatile uint32_t RSVD_2563;	 // 0x2854 Reserved 2563.
	volatile uint32_t RSVD_2564;	 // 0x2858 Reserved 2564.
	volatile uint32_t RSVD_2565;	 // 0x285c Reserved 2565.
	volatile uint32_t RSVD_2566;	 // 0x2860 Reserved 2566.
	volatile uint32_t RSVD_2567;	 // 0x2864 Reserved 2567.
	volatile uint32_t RSVD_2568;	 // 0x2868 Reserved 2568.
	volatile uint32_t RSVD_2569;	 // 0x286c Reserved 2569.
	volatile uint32_t RSVD_2570;	 // 0x2870 Reserved 2570.
	volatile uint32_t RSVD_2571;	 // 0x2874 Reserved 2571.
	volatile uint32_t RSVD_2572;	 // 0x2878 Reserved 2572.
	volatile uint32_t RSVD_2573;	 // 0x287c Reserved 2573.
	volatile uint32_t RSVD_2574;	 // 0x2880 Reserved 2574.
	volatile uint32_t RSVD_2575;	 // 0x2884 Reserved 2575.
	volatile uint32_t RSVD_2576;	 // 0x2888 Reserved 2576.
	volatile uint32_t RSVD_2577;	 // 0x288c Reserved 2577.
	volatile uint32_t RSVD_2578;	 // 0x2890 Reserved 2578.
	volatile uint32_t RSVD_2579;	 // 0x2894 Reserved 2579.
	volatile uint32_t RSVD_2580;	 // 0x2898 Reserved 2580.
	volatile uint32_t RSVD_2581;	 // 0x289c Reserved 2581.
	volatile uint32_t RSVD_2582;	 // 0x28a0 Reserved 2582.
	volatile uint32_t RSVD_2583;	 // 0x28a4 Reserved 2583.
	volatile uint32_t RSVD_2584;	 // 0x28a8 Reserved 2584.
	volatile uint32_t RSVD_2585;	 // 0x28ac Reserved 2585.
	volatile uint32_t RSVD_2586;	 // 0x28b0 Reserved 2586.
	volatile uint32_t RSVD_2587;	 // 0x28b4 Reserved 2587.
	volatile uint32_t RSVD_2588;	 // 0x28b8 Reserved 2588.
	volatile uint32_t RSVD_2589;	 // 0x28bc Reserved 2589.
	volatile uint32_t RSVD_2590;	 // 0x28c0 Reserved 2590.
	volatile uint32_t RSVD_2591;	 // 0x28c4 Reserved 2591.
	volatile uint32_t RSVD_2592;	 // 0x28c8 Reserved 2592.
	volatile uint32_t RSVD_2593;	 // 0x28cc Reserved 2593.
	volatile uint32_t RSVD_2594;	 // 0x28d0 Reserved 2594.
	volatile uint32_t RSVD_2595;	 // 0x28d4 Reserved 2595.
	volatile uint32_t RSVD_2596;	 // 0x28d8 Reserved 2596.
	volatile uint32_t RSVD_2597;	 // 0x28dc Reserved 2597.
	volatile uint32_t RSVD_2598;	 // 0x28e0 Reserved 2598.
	volatile uint32_t RSVD_2599;	 // 0x28e4 Reserved 2599.
	volatile uint32_t RSVD_2600;	 // 0x28e8 Reserved 2600.
	volatile uint32_t RSVD_2601;	 // 0x28ec Reserved 2601.
	volatile uint32_t RSVD_2602;	 // 0x28f0 Reserved 2602.
	volatile uint32_t RSVD_2603;	 // 0x28f4 Reserved 2603.
	volatile uint32_t RSVD_2604;	 // 0x28f8 Reserved 2604.
	volatile uint32_t RSVD_2605;	 // 0x28fc Reserved 2605.
	volatile uint32_t RSVD_2606;	 // 0x2900 Reserved 2606.
	volatile uint32_t RSVD_2607;	 // 0x2904 Reserved 2607.
	volatile uint32_t RSVD_2608;	 // 0x2908 Reserved 2608.
	volatile uint32_t RSVD_2609;	 // 0x290c Reserved 2609.
	volatile uint32_t RSVD_2610;	 // 0x2910 Reserved 2610.
	volatile uint32_t RSVD_2611;	 // 0x2914 Reserved 2611.
	volatile uint32_t RSVD_2612;	 // 0x2918 Reserved 2612.
	volatile uint32_t RSVD_2613;	 // 0x291c Reserved 2613.
	volatile uint32_t RSVD_2614;	 // 0x2920 Reserved 2614.
	volatile uint32_t RSVD_2615;	 // 0x2924 Reserved 2615.
	volatile uint32_t RSVD_2616;	 // 0x2928 Reserved 2616.
	volatile uint32_t RSVD_2617;	 // 0x292c Reserved 2617.
	volatile uint32_t RSVD_2618;	 // 0x2930 Reserved 2618.
	volatile uint32_t RSVD_2619;	 // 0x2934 Reserved 2619.
	volatile uint32_t RSVD_2620;	 // 0x2938 Reserved 2620.
	volatile uint32_t RSVD_2621;	 // 0x293c Reserved 2621.
	volatile uint32_t RSVD_2622;	 // 0x2940 Reserved 2622.
	volatile uint32_t RSVD_2623;	 // 0x2944 Reserved 2623.
	volatile uint32_t RSVD_2624;	 // 0x2948 Reserved 2624.
	volatile uint32_t RSVD_2625;	 // 0x294c Reserved 2625.
	volatile uint32_t RSVD_2626;	 // 0x2950 Reserved 2626.
	volatile uint32_t RSVD_2627;	 // 0x2954 Reserved 2627.
	volatile uint32_t RSVD_2628;	 // 0x2958 Reserved 2628.
	volatile uint32_t RSVD_2629;	 // 0x295c Reserved 2629.
	volatile uint32_t RSVD_2630;	 // 0x2960 Reserved 2630.
	volatile uint32_t RSVD_2631;	 // 0x2964 Reserved 2631.
	volatile uint32_t RSVD_2632;	 // 0x2968 Reserved 2632.
	volatile uint32_t RSVD_2633;	 // 0x296c Reserved 2633.
	volatile uint32_t RSVD_2634;	 // 0x2970 Reserved 2634.
	volatile uint32_t RSVD_2635;	 // 0x2974 Reserved 2635.
	volatile uint32_t RSVD_2636;	 // 0x2978 Reserved 2636.
	volatile uint32_t RSVD_2637;	 // 0x297c Reserved 2637.
	volatile uint32_t RSVD_2638;	 // 0x2980 Reserved 2638.
	volatile uint32_t RSVD_2639;	 // 0x2984 Reserved 2639.
	volatile uint32_t RSVD_2640;	 // 0x2988 Reserved 2640.
	volatile uint32_t RSVD_2641;	 // 0x298c Reserved 2641.
	volatile uint32_t RSVD_2642;	 // 0x2990 Reserved 2642.
	volatile uint32_t RSVD_2643;	 // 0x2994 Reserved 2643.
	volatile uint32_t RSVD_2644;	 // 0x2998 Reserved 2644.
	volatile uint32_t RSVD_2645;	 // 0x299c Reserved 2645.
	volatile uint32_t RSVD_2646;	 // 0x29a0 Reserved 2646.
	volatile uint32_t RSVD_2647;	 // 0x29a4 Reserved 2647.
	volatile uint32_t RSVD_2648;	 // 0x29a8 Reserved 2648.
	volatile uint32_t RSVD_2649;	 // 0x29ac Reserved 2649.
	volatile uint32_t RSVD_2650;	 // 0x29b0 Reserved 2650.
	volatile uint32_t RSVD_2651;	 // 0x29b4 Reserved 2651.
	volatile uint32_t RSVD_2652;	 // 0x29b8 Reserved 2652.
	volatile uint32_t RSVD_2653;	 // 0x29bc Reserved 2653.
	volatile uint32_t RSVD_2654;	 // 0x29c0 Reserved 2654.
	volatile uint32_t RSVD_2655;	 // 0x29c4 Reserved 2655.
	volatile uint32_t RSVD_2656;	 // 0x29c8 Reserved 2656.
	volatile uint32_t RSVD_2657;	 // 0x29cc Reserved 2657.
	volatile uint32_t RSVD_2658;	 // 0x29d0 Reserved 2658.
	volatile uint32_t RSVD_2659;	 // 0x29d4 Reserved 2659.
	volatile uint32_t RSVD_2660;	 // 0x29d8 Reserved 2660.
	volatile uint32_t RSVD_2661;	 // 0x29dc Reserved 2661.
	volatile uint32_t RSVD_2662;	 // 0x29e0 Reserved 2662.
	volatile uint32_t RSVD_2663;	 // 0x29e4 Reserved 2663.
	volatile uint32_t RSVD_2664;	 // 0x29e8 Reserved 2664.
	volatile uint32_t RSVD_2665;	 // 0x29ec Reserved 2665.
	volatile uint32_t RSVD_2666;	 // 0x29f0 Reserved 2666.
	volatile uint32_t RSVD_2667;	 // 0x29f4 Reserved 2667.
	volatile uint32_t RSVD_2668;	 // 0x29f8 Reserved 2668.
	volatile uint32_t RSVD_2669;	 // 0x29fc Reserved 2669.
	volatile uint32_t RSVD_2670;	 // 0x2a00 Reserved 2670.
	volatile uint32_t RSVD_2671;	 // 0x2a04 Reserved 2671.
	volatile uint32_t RSVD_2672;	 // 0x2a08 Reserved 2672.
	volatile uint32_t RSVD_2673;	 // 0x2a0c Reserved 2673.
	volatile uint32_t RSVD_2674;	 // 0x2a10 Reserved 2674.
	volatile uint32_t RSVD_2675;	 // 0x2a14 Reserved 2675.
	volatile uint32_t RSVD_2676;	 // 0x2a18 Reserved 2676.
	volatile uint32_t RSVD_2677;	 // 0x2a1c Reserved 2677.
	volatile uint32_t RSVD_2678;	 // 0x2a20 Reserved 2678.
	volatile uint32_t RSVD_2679;	 // 0x2a24 Reserved 2679.
	volatile uint32_t RSVD_2680;	 // 0x2a28 Reserved 2680.
	volatile uint32_t RSVD_2681;	 // 0x2a2c Reserved 2681.
	volatile uint32_t RSVD_2682;	 // 0x2a30 Reserved 2682.
	volatile uint32_t RSVD_2683;	 // 0x2a34 Reserved 2683.
	volatile uint32_t RSVD_2684;	 // 0x2a38 Reserved 2684.
	volatile uint32_t RSVD_2685;	 // 0x2a3c Reserved 2685.
	volatile uint32_t RSVD_2686;	 // 0x2a40 Reserved 2686.
	volatile uint32_t RSVD_2687;	 // 0x2a44 Reserved 2687.
	volatile uint32_t RSVD_2688;	 // 0x2a48 Reserved 2688.
	volatile uint32_t RSVD_2689;	 // 0x2a4c Reserved 2689.
	volatile uint32_t RSVD_2690;	 // 0x2a50 Reserved 2690.
	volatile uint32_t RSVD_2691;	 // 0x2a54 Reserved 2691.
	volatile uint32_t RSVD_2692;	 // 0x2a58 Reserved 2692.
	volatile uint32_t RSVD_2693;	 // 0x2a5c Reserved 2693.
	volatile uint32_t RSVD_2694;	 // 0x2a60 Reserved 2694.
	volatile uint32_t RSVD_2695;	 // 0x2a64 Reserved 2695.
	volatile uint32_t RSVD_2696;	 // 0x2a68 Reserved 2696.
	volatile uint32_t RSVD_2697;	 // 0x2a6c Reserved 2697.
	volatile uint32_t RSVD_2698;	 // 0x2a70 Reserved 2698.
	volatile uint32_t RSVD_2699;	 // 0x2a74 Reserved 2699.
	volatile uint32_t RSVD_2700;	 // 0x2a78 Reserved 2700.
	volatile uint32_t RSVD_2701;	 // 0x2a7c Reserved 2701.
	volatile uint32_t RSVD_2702;	 // 0x2a80 Reserved 2702.
	volatile uint32_t RSVD_2703;	 // 0x2a84 Reserved 2703.
	volatile uint32_t RSVD_2704;	 // 0x2a88 Reserved 2704.
	volatile uint32_t RSVD_2705;	 // 0x2a8c Reserved 2705.
	volatile uint32_t RSVD_2706;	 // 0x2a90 Reserved 2706.
	volatile uint32_t RSVD_2707;	 // 0x2a94 Reserved 2707.
	volatile uint32_t RSVD_2708;	 // 0x2a98 Reserved 2708.
	volatile uint32_t RSVD_2709;	 // 0x2a9c Reserved 2709.
	volatile uint32_t RSVD_2710;	 // 0x2aa0 Reserved 2710.
	volatile uint32_t RSVD_2711;	 // 0x2aa4 Reserved 2711.
	volatile uint32_t RSVD_2712;	 // 0x2aa8 Reserved 2712.
	volatile uint32_t RSVD_2713;	 // 0x2aac Reserved 2713.
	volatile uint32_t RSVD_2714;	 // 0x2ab0 Reserved 2714.
	volatile uint32_t RSVD_2715;	 // 0x2ab4 Reserved 2715.
	volatile uint32_t RSVD_2716;	 // 0x2ab8 Reserved 2716.
	volatile uint32_t RSVD_2717;	 // 0x2abc Reserved 2717.
	volatile uint32_t RSVD_2718;	 // 0x2ac0 Reserved 2718.
	volatile uint32_t RSVD_2719;	 // 0x2ac4 Reserved 2719.
	volatile uint32_t RSVD_2720;	 // 0x2ac8 Reserved 2720.
	volatile uint32_t RSVD_2721;	 // 0x2acc Reserved 2721.
	volatile uint32_t RSVD_2722;	 // 0x2ad0 Reserved 2722.
	volatile uint32_t RSVD_2723;	 // 0x2ad4 Reserved 2723.
	volatile uint32_t RSVD_2724;	 // 0x2ad8 Reserved 2724.
	volatile uint32_t RSVD_2725;	 // 0x2adc Reserved 2725.
	volatile uint32_t RSVD_2726;	 // 0x2ae0 Reserved 2726.
	volatile uint32_t RSVD_2727;	 // 0x2ae4 Reserved 2727.
	volatile uint32_t RSVD_2728;	 // 0x2ae8 Reserved 2728.
	volatile uint32_t RSVD_2729;	 // 0x2aec Reserved 2729.
	volatile uint32_t RSVD_2730;	 // 0x2af0 Reserved 2730.
	volatile uint32_t RSVD_2731;	 // 0x2af4 Reserved 2731.
	volatile uint32_t RSVD_2732;	 // 0x2af8 Reserved 2732.
	volatile uint32_t RSVD_2733;	 // 0x2afc Reserved 2733.
	volatile uint32_t RSVD_2734;	 // 0x2b00 Reserved 2734.
	volatile uint32_t RSVD_2735;	 // 0x2b04 Reserved 2735.
	volatile uint32_t RSVD_2736;	 // 0x2b08 Reserved 2736.
	volatile uint32_t RSVD_2737;	 // 0x2b0c Reserved 2737.
	volatile uint32_t RSVD_2738;	 // 0x2b10 Reserved 2738.
	volatile uint32_t RSVD_2739;	 // 0x2b14 Reserved 2739.
	volatile uint32_t RSVD_2740;	 // 0x2b18 Reserved 2740.
	volatile uint32_t RSVD_2741;	 // 0x2b1c Reserved 2741.
	volatile uint32_t RSVD_2742;	 // 0x2b20 Reserved 2742.
	volatile uint32_t RSVD_2743;	 // 0x2b24 Reserved 2743.
	volatile uint32_t RSVD_2744;	 // 0x2b28 Reserved 2744.
	volatile uint32_t RSVD_2745;	 // 0x2b2c Reserved 2745.
	volatile uint32_t RSVD_2746;	 // 0x2b30 Reserved 2746.
	volatile uint32_t RSVD_2747;	 // 0x2b34 Reserved 2747.
	volatile uint32_t RSVD_2748;	 // 0x2b38 Reserved 2748.
	volatile uint32_t RSVD_2749;	 // 0x2b3c Reserved 2749.
	volatile uint32_t RSVD_2750;	 // 0x2b40 Reserved 2750.
	volatile uint32_t RSVD_2751;	 // 0x2b44 Reserved 2751.
	volatile uint32_t RSVD_2752;	 // 0x2b48 Reserved 2752.
	volatile uint32_t RSVD_2753;	 // 0x2b4c Reserved 2753.
	volatile uint32_t RSVD_2754;	 // 0x2b50 Reserved 2754.
	volatile uint32_t RSVD_2755;	 // 0x2b54 Reserved 2755.
	volatile uint32_t RSVD_2756;	 // 0x2b58 Reserved 2756.
	volatile uint32_t RSVD_2757;	 // 0x2b5c Reserved 2757.
	volatile uint32_t RSVD_2758;	 // 0x2b60 Reserved 2758.
	volatile uint32_t RSVD_2759;	 // 0x2b64 Reserved 2759.
	volatile uint32_t RSVD_2760;	 // 0x2b68 Reserved 2760.
	volatile uint32_t RSVD_2761;	 // 0x2b6c Reserved 2761.
	volatile uint32_t RSVD_2762;	 // 0x2b70 Reserved 2762.
	volatile uint32_t RSVD_2763;	 // 0x2b74 Reserved 2763.
	volatile uint32_t RSVD_2764;	 // 0x2b78 Reserved 2764.
	volatile uint32_t RSVD_2765;	 // 0x2b7c Reserved 2765.
	volatile uint32_t RSVD_2766;	 // 0x2b80 Reserved 2766.
	volatile uint32_t RSVD_2767;	 // 0x2b84 Reserved 2767.
	volatile uint32_t RSVD_2768;	 // 0x2b88 Reserved 2768.
	volatile uint32_t RSVD_2769;	 // 0x2b8c Reserved 2769.
	volatile uint32_t RSVD_2770;	 // 0x2b90 Reserved 2770.
	volatile uint32_t RSVD_2771;	 // 0x2b94 Reserved 2771.
	volatile uint32_t RSVD_2772;	 // 0x2b98 Reserved 2772.
	volatile uint32_t RSVD_2773;	 // 0x2b9c Reserved 2773.
	volatile uint32_t RSVD_2774;	 // 0x2ba0 Reserved 2774.
	volatile uint32_t RSVD_2775;	 // 0x2ba4 Reserved 2775.
	volatile uint32_t RSVD_2776;	 // 0x2ba8 Reserved 2776.
	volatile uint32_t RSVD_2777;	 // 0x2bac Reserved 2777.
	volatile uint32_t RSVD_2778;	 // 0x2bb0 Reserved 2778.
	volatile uint32_t RSVD_2779;	 // 0x2bb4 Reserved 2779.
	volatile uint32_t RSVD_2780;	 // 0x2bb8 Reserved 2780.
	volatile uint32_t RSVD_2781;	 // 0x2bbc Reserved 2781.
	volatile uint32_t RSVD_2782;	 // 0x2bc0 Reserved 2782.
	volatile uint32_t RSVD_2783;	 // 0x2bc4 Reserved 2783.
	volatile uint32_t RSVD_2784;	 // 0x2bc8 Reserved 2784.
	volatile uint32_t RSVD_2785;	 // 0x2bcc Reserved 2785.
	volatile uint32_t RSVD_2786;	 // 0x2bd0 Reserved 2786.
	volatile uint32_t RSVD_2787;	 // 0x2bd4 Reserved 2787.
	volatile uint32_t RSVD_2788;	 // 0x2bd8 Reserved 2788.
	volatile uint32_t RSVD_2789;	 // 0x2bdc Reserved 2789.
	volatile uint32_t RSVD_2790;	 // 0x2be0 Reserved 2790.
	volatile uint32_t RSVD_2791;	 // 0x2be4 Reserved 2791.
	volatile uint32_t RSVD_2792;	 // 0x2be8 Reserved 2792.
	volatile uint32_t RSVD_2793;	 // 0x2bec Reserved 2793.
	volatile uint32_t RSVD_2794;	 // 0x2bf0 Reserved 2794.
	volatile uint32_t RSVD_2795;	 // 0x2bf4 Reserved 2795.
	volatile uint32_t RSVD_2796;	 // 0x2bf8 Reserved 2796.
	volatile uint32_t RSVD_2797;	 // 0x2bfc Reserved 2797.
	volatile uint32_t RSVD_2798;	 // 0x2c00 Reserved 2798.
	volatile uint32_t RSVD_2799;	 // 0x2c04 Reserved 2799.
	volatile uint32_t RSVD_2800;	 // 0x2c08 Reserved 2800.
	volatile uint32_t RSVD_2801;	 // 0x2c0c Reserved 2801.
	volatile uint32_t RSVD_2802;	 // 0x2c10 Reserved 2802.
	volatile uint32_t RSVD_2803;	 // 0x2c14 Reserved 2803.
	volatile uint32_t RSVD_2804;	 // 0x2c18 Reserved 2804.
	volatile uint32_t RSVD_2805;	 // 0x2c1c Reserved 2805.
	volatile uint32_t RSVD_2806;	 // 0x2c20 Reserved 2806.
	volatile uint32_t RSVD_2807;	 // 0x2c24 Reserved 2807.
	volatile uint32_t RSVD_2808;	 // 0x2c28 Reserved 2808.
	volatile uint32_t RSVD_2809;	 // 0x2c2c Reserved 2809.
	volatile uint32_t RSVD_2810;	 // 0x2c30 Reserved 2810.
	volatile uint32_t RSVD_2811;	 // 0x2c34 Reserved 2811.
	volatile uint32_t RSVD_2812;	 // 0x2c38 Reserved 2812.
	volatile uint32_t RSVD_2813;	 // 0x2c3c Reserved 2813.
	volatile uint32_t RSVD_2814;	 // 0x2c40 Reserved 2814.
	volatile uint32_t RSVD_2815;	 // 0x2c44 Reserved 2815.
	volatile uint32_t RSVD_2816;	 // 0x2c48 Reserved 2816.
	volatile uint32_t RSVD_2817;	 // 0x2c4c Reserved 2817.
	volatile uint32_t RSVD_2818;	 // 0x2c50 Reserved 2818.
	volatile uint32_t RSVD_2819;	 // 0x2c54 Reserved 2819.
	volatile uint32_t RSVD_2820;	 // 0x2c58 Reserved 2820.
	volatile uint32_t RSVD_2821;	 // 0x2c5c Reserved 2821.
	volatile uint32_t RSVD_2822;	 // 0x2c60 Reserved 2822.
	volatile uint32_t RSVD_2823;	 // 0x2c64 Reserved 2823.
	volatile uint32_t RSVD_2824;	 // 0x2c68 Reserved 2824.
	volatile uint32_t RSVD_2825;	 // 0x2c6c Reserved 2825.
	volatile uint32_t RSVD_2826;	 // 0x2c70 Reserved 2826.
	volatile uint32_t RSVD_2827;	 // 0x2c74 Reserved 2827.
	volatile uint32_t RSVD_2828;	 // 0x2c78 Reserved 2828.
	volatile uint32_t RSVD_2829;	 // 0x2c7c Reserved 2829.
	volatile uint32_t RSVD_2830;	 // 0x2c80 Reserved 2830.
	volatile uint32_t RSVD_2831;	 // 0x2c84 Reserved 2831.
	volatile uint32_t RSVD_2832;	 // 0x2c88 Reserved 2832.
	volatile uint32_t RSVD_2833;	 // 0x2c8c Reserved 2833.
	volatile uint32_t RSVD_2834;	 // 0x2c90 Reserved 2834.
	volatile uint32_t RSVD_2835;	 // 0x2c94 Reserved 2835.
	volatile uint32_t RSVD_2836;	 // 0x2c98 Reserved 2836.
	volatile uint32_t RSVD_2837;	 // 0x2c9c Reserved 2837.
	volatile uint32_t RSVD_2838;	 // 0x2ca0 Reserved 2838.
	volatile uint32_t RSVD_2839;	 // 0x2ca4 Reserved 2839.
	volatile uint32_t RSVD_2840;	 // 0x2ca8 Reserved 2840.
	volatile uint32_t RSVD_2841;	 // 0x2cac Reserved 2841.
	volatile uint32_t RSVD_2842;	 // 0x2cb0 Reserved 2842.
	volatile uint32_t RSVD_2843;	 // 0x2cb4 Reserved 2843.
	volatile uint32_t RSVD_2844;	 // 0x2cb8 Reserved 2844.
	volatile uint32_t RSVD_2845;	 // 0x2cbc Reserved 2845.
	volatile uint32_t RSVD_2846;	 // 0x2cc0 Reserved 2846.
	volatile uint32_t RSVD_2847;	 // 0x2cc4 Reserved 2847.
	volatile uint32_t RSVD_2848;	 // 0x2cc8 Reserved 2848.
	volatile uint32_t RSVD_2849;	 // 0x2ccc Reserved 2849.
	volatile uint32_t RSVD_2850;	 // 0x2cd0 Reserved 2850.
	volatile uint32_t RSVD_2851;	 // 0x2cd4 Reserved 2851.
	volatile uint32_t RSVD_2852;	 // 0x2cd8 Reserved 2852.
	volatile uint32_t RSVD_2853;	 // 0x2cdc Reserved 2853.
	volatile uint32_t RSVD_2854;	 // 0x2ce0 Reserved 2854.
	volatile uint32_t RSVD_2855;	 // 0x2ce4 Reserved 2855.
	volatile uint32_t RSVD_2856;	 // 0x2ce8 Reserved 2856.
	volatile uint32_t RSVD_2857;	 // 0x2cec Reserved 2857.
	volatile uint32_t RSVD_2858;	 // 0x2cf0 Reserved 2858.
	volatile uint32_t RSVD_2859;	 // 0x2cf4 Reserved 2859.
	volatile uint32_t RSVD_2860;	 // 0x2cf8 Reserved 2860.
	volatile uint32_t RSVD_2861;	 // 0x2cfc Reserved 2861.
	volatile uint32_t RSVD_2862;	 // 0x2d00 Reserved 2862.
	volatile uint32_t RSVD_2863;	 // 0x2d04 Reserved 2863.
	volatile uint32_t RSVD_2864;	 // 0x2d08 Reserved 2864.
	volatile uint32_t RSVD_2865;	 // 0x2d0c Reserved 2865.
	volatile uint32_t RSVD_2866;	 // 0x2d10 Reserved 2866.
	volatile uint32_t RSVD_2867;	 // 0x2d14 Reserved 2867.
	volatile uint32_t RSVD_2868;	 // 0x2d18 Reserved 2868.
	volatile uint32_t RSVD_2869;	 // 0x2d1c Reserved 2869.
	volatile uint32_t RSVD_2870;	 // 0x2d20 Reserved 2870.
	volatile uint32_t RSVD_2871;	 // 0x2d24 Reserved 2871.
	volatile uint32_t RSVD_2872;	 // 0x2d28 Reserved 2872.
	volatile uint32_t RSVD_2873;	 // 0x2d2c Reserved 2873.
	volatile uint32_t RSVD_2874;	 // 0x2d30 Reserved 2874.
	volatile uint32_t RSVD_2875;	 // 0x2d34 Reserved 2875.
	volatile uint32_t RSVD_2876;	 // 0x2d38 Reserved 2876.
	volatile uint32_t RSVD_2877;	 // 0x2d3c Reserved 2877.
	volatile uint32_t RSVD_2878;	 // 0x2d40 Reserved 2878.
	volatile uint32_t RSVD_2879;	 // 0x2d44 Reserved 2879.
	volatile uint32_t RSVD_2880;	 // 0x2d48 Reserved 2880.
	volatile uint32_t RSVD_2881;	 // 0x2d4c Reserved 2881.
	volatile uint32_t RSVD_2882;	 // 0x2d50 Reserved 2882.
	volatile uint32_t RSVD_2883;	 // 0x2d54 Reserved 2883.
	volatile uint32_t RSVD_2884;	 // 0x2d58 Reserved 2884.
	volatile uint32_t RSVD_2885;	 // 0x2d5c Reserved 2885.
	volatile uint32_t RSVD_2886;	 // 0x2d60 Reserved 2886.
	volatile uint32_t RSVD_2887;	 // 0x2d64 Reserved 2887.
	volatile uint32_t RSVD_2888;	 // 0x2d68 Reserved 2888.
	volatile uint32_t RSVD_2889;	 // 0x2d6c Reserved 2889.
	volatile uint32_t RSVD_2890;	 // 0x2d70 Reserved 2890.
	volatile uint32_t RSVD_2891;	 // 0x2d74 Reserved 2891.
	volatile uint32_t RSVD_2892;	 // 0x2d78 Reserved 2892.
	volatile uint32_t RSVD_2893;	 // 0x2d7c Reserved 2893.
	volatile uint32_t RSVD_2894;	 // 0x2d80 Reserved 2894.
	volatile uint32_t RSVD_2895;	 // 0x2d84 Reserved 2895.
	volatile uint32_t RSVD_2896;	 // 0x2d88 Reserved 2896.
	volatile uint32_t RSVD_2897;	 // 0x2d8c Reserved 2897.
	volatile uint32_t RSVD_2898;	 // 0x2d90 Reserved 2898.
	volatile uint32_t RSVD_2899;	 // 0x2d94 Reserved 2899.
	volatile uint32_t RSVD_2900;	 // 0x2d98 Reserved 2900.
	volatile uint32_t RSVD_2901;	 // 0x2d9c Reserved 2901.
	volatile uint32_t RSVD_2902;	 // 0x2da0 Reserved 2902.
	volatile uint32_t RSVD_2903;	 // 0x2da4 Reserved 2903.
	volatile uint32_t RSVD_2904;	 // 0x2da8 Reserved 2904.
	volatile uint32_t RSVD_2905;	 // 0x2dac Reserved 2905.
	volatile uint32_t RSVD_2906;	 // 0x2db0 Reserved 2906.
	volatile uint32_t RSVD_2907;	 // 0x2db4 Reserved 2907.
	volatile uint32_t RSVD_2908;	 // 0x2db8 Reserved 2908.
	volatile uint32_t RSVD_2909;	 // 0x2dbc Reserved 2909.
	volatile uint32_t RSVD_2910;	 // 0x2dc0 Reserved 2910.
	volatile uint32_t RSVD_2911;	 // 0x2dc4 Reserved 2911.
	volatile uint32_t RSVD_2912;	 // 0x2dc8 Reserved 2912.
	volatile uint32_t RSVD_2913;	 // 0x2dcc Reserved 2913.
	volatile uint32_t RSVD_2914;	 // 0x2dd0 Reserved 2914.
	volatile uint32_t RSVD_2915;	 // 0x2dd4 Reserved 2915.
	volatile uint32_t RSVD_2916;	 // 0x2dd8 Reserved 2916.
	volatile uint32_t RSVD_2917;	 // 0x2ddc Reserved 2917.
	volatile uint32_t RSVD_2918;	 // 0x2de0 Reserved 2918.
	volatile uint32_t RSVD_2919;	 // 0x2de4 Reserved 2919.
	volatile uint32_t RSVD_2920;	 // 0x2de8 Reserved 2920.
	volatile uint32_t RSVD_2921;	 // 0x2dec Reserved 2921.
	volatile uint32_t RSVD_2922;	 // 0x2df0 Reserved 2922.
	volatile uint32_t RSVD_2923;	 // 0x2df4 Reserved 2923.
	volatile uint32_t RSVD_2924;	 // 0x2df8 Reserved 2924.
	volatile uint32_t RSVD_2925;	 // 0x2dfc Reserved 2925.
	volatile uint32_t RSVD_2926;	 // 0x2e00 Reserved 2926.
	volatile uint32_t RSVD_2927;	 // 0x2e04 Reserved 2927.
	volatile uint32_t RSVD_2928;	 // 0x2e08 Reserved 2928.
	volatile uint32_t RSVD_2929;	 // 0x2e0c Reserved 2929.
	volatile uint32_t RSVD_2930;	 // 0x2e10 Reserved 2930.
	volatile uint32_t RSVD_2931;	 // 0x2e14 Reserved 2931.
	volatile uint32_t RSVD_2932;	 // 0x2e18 Reserved 2932.
	volatile uint32_t RSVD_2933;	 // 0x2e1c Reserved 2933.
	volatile uint32_t RSVD_2934;	 // 0x2e20 Reserved 2934.
	volatile uint32_t RSVD_2935;	 // 0x2e24 Reserved 2935.
	volatile uint32_t RSVD_2936;	 // 0x2e28 Reserved 2936.
	volatile uint32_t RSVD_2937;	 // 0x2e2c Reserved 2937.
	volatile uint32_t RSVD_2938;	 // 0x2e30 Reserved 2938.
	volatile uint32_t RSVD_2939;	 // 0x2e34 Reserved 2939.
	volatile uint32_t RSVD_2940;	 // 0x2e38 Reserved 2940.
	volatile uint32_t RSVD_2941;	 // 0x2e3c Reserved 2941.
	volatile uint32_t RSVD_2942;	 // 0x2e40 Reserved 2942.
	volatile uint32_t RSVD_2943;	 // 0x2e44 Reserved 2943.
	volatile uint32_t RSVD_2944;	 // 0x2e48 Reserved 2944.
	volatile uint32_t RSVD_2945;	 // 0x2e4c Reserved 2945.
	volatile uint32_t RSVD_2946;	 // 0x2e50 Reserved 2946.
	volatile uint32_t RSVD_2947;	 // 0x2e54 Reserved 2947.
	volatile uint32_t RSVD_2948;	 // 0x2e58 Reserved 2948.
	volatile uint32_t RSVD_2949;	 // 0x2e5c Reserved 2949.
	volatile uint32_t RSVD_2950;	 // 0x2e60 Reserved 2950.
	volatile uint32_t RSVD_2951;	 // 0x2e64 Reserved 2951.
	volatile uint32_t RSVD_2952;	 // 0x2e68 Reserved 2952.
	volatile uint32_t RSVD_2953;	 // 0x2e6c Reserved 2953.
	volatile uint32_t RSVD_2954;	 // 0x2e70 Reserved 2954.
	volatile uint32_t RSVD_2955;	 // 0x2e74 Reserved 2955.
	volatile uint32_t RSVD_2956;	 // 0x2e78 Reserved 2956.
	volatile uint32_t RSVD_2957;	 // 0x2e7c Reserved 2957.
	volatile uint32_t RSVD_2958;	 // 0x2e80 Reserved 2958.
	volatile uint32_t RSVD_2959;	 // 0x2e84 Reserved 2959.
	volatile uint32_t RSVD_2960;	 // 0x2e88 Reserved 2960.
	volatile uint32_t RSVD_2961;	 // 0x2e8c Reserved 2961.
	volatile uint32_t RSVD_2962;	 // 0x2e90 Reserved 2962.
	volatile uint32_t RSVD_2963;	 // 0x2e94 Reserved 2963.
	volatile uint32_t RSVD_2964;	 // 0x2e98 Reserved 2964.
	volatile uint32_t RSVD_2965;	 // 0x2e9c Reserved 2965.
	volatile uint32_t RSVD_2966;	 // 0x2ea0 Reserved 2966.
	volatile uint32_t RSVD_2967;	 // 0x2ea4 Reserved 2967.
	volatile uint32_t RSVD_2968;	 // 0x2ea8 Reserved 2968.
	volatile uint32_t RSVD_2969;	 // 0x2eac Reserved 2969.
	volatile uint32_t RSVD_2970;	 // 0x2eb0 Reserved 2970.
	volatile uint32_t RSVD_2971;	 // 0x2eb4 Reserved 2971.
	volatile uint32_t RSVD_2972;	 // 0x2eb8 Reserved 2972.
	volatile uint32_t RSVD_2973;	 // 0x2ebc Reserved 2973.
	volatile uint32_t RSVD_2974;	 // 0x2ec0 Reserved 2974.
	volatile uint32_t RSVD_2975;	 // 0x2ec4 Reserved 2975.
	volatile uint32_t RSVD_2976;	 // 0x2ec8 Reserved 2976.
	volatile uint32_t RSVD_2977;	 // 0x2ecc Reserved 2977.
	volatile uint32_t RSVD_2978;	 // 0x2ed0 Reserved 2978.
	volatile uint32_t RSVD_2979;	 // 0x2ed4 Reserved 2979.
	volatile uint32_t RSVD_2980;	 // 0x2ed8 Reserved 2980.
	volatile uint32_t RSVD_2981;	 // 0x2edc Reserved 2981.
	volatile uint32_t RSVD_2982;	 // 0x2ee0 Reserved 2982.
	volatile uint32_t RSVD_2983;	 // 0x2ee4 Reserved 2983.
	volatile uint32_t RSVD_2984;	 // 0x2ee8 Reserved 2984.
	volatile uint32_t RSVD_2985;	 // 0x2eec Reserved 2985.
	volatile uint32_t RSVD_2986;	 // 0x2ef0 Reserved 2986.
	volatile uint32_t RSVD_2987;	 // 0x2ef4 Reserved 2987.
	volatile uint32_t RSVD_2988;	 // 0x2ef8 Reserved 2988.
	volatile uint32_t RSVD_2989;	 // 0x2efc Reserved 2989.
	volatile uint32_t RSVD_2990;	 // 0x2f00 Reserved 2990.
	volatile uint32_t RSVD_2991;	 // 0x2f04 Reserved 2991.
	volatile uint32_t RSVD_2992;	 // 0x2f08 Reserved 2992.
	volatile uint32_t RSVD_2993;	 // 0x2f0c Reserved 2993.
	volatile uint32_t RSVD_2994;	 // 0x2f10 Reserved 2994.
	volatile uint32_t RSVD_2995;	 // 0x2f14 Reserved 2995.
	volatile uint32_t RSVD_2996;	 // 0x2f18 Reserved 2996.
	volatile uint32_t RSVD_2997;	 // 0x2f1c Reserved 2997.
	volatile uint32_t RSVD_2998;	 // 0x2f20 Reserved 2998.
	volatile uint32_t RSVD_2999;	 // 0x2f24 Reserved 2999.
	volatile uint32_t RSVD_3000;	 // 0x2f28 Reserved 3000.
	volatile uint32_t RSVD_3001;	 // 0x2f2c Reserved 3001.
	volatile uint32_t RSVD_3002;	 // 0x2f30 Reserved 3002.
	volatile uint32_t RSVD_3003;	 // 0x2f34 Reserved 3003.
	volatile uint32_t RSVD_3004;	 // 0x2f38 Reserved 3004.
	volatile uint32_t RSVD_3005;	 // 0x2f3c Reserved 3005.
	volatile uint32_t RSVD_3006;	 // 0x2f40 Reserved 3006.
	volatile uint32_t RSVD_3007;	 // 0x2f44 Reserved 3007.
	volatile uint32_t RSVD_3008;	 // 0x2f48 Reserved 3008.
	volatile uint32_t RSVD_3009;	 // 0x2f4c Reserved 3009.
	volatile uint32_t RSVD_3010;	 // 0x2f50 Reserved 3010.
	volatile uint32_t RSVD_3011;	 // 0x2f54 Reserved 3011.
	volatile uint32_t RSVD_3012;	 // 0x2f58 Reserved 3012.
	volatile uint32_t RSVD_3013;	 // 0x2f5c Reserved 3013.
	volatile uint32_t RSVD_3014;	 // 0x2f60 Reserved 3014.
	volatile uint32_t RSVD_3015;	 // 0x2f64 Reserved 3015.
	volatile uint32_t RSVD_3016;	 // 0x2f68 Reserved 3016.
	volatile uint32_t RSVD_3017;	 // 0x2f6c Reserved 3017.
	volatile uint32_t RSVD_3018;	 // 0x2f70 Reserved 3018.
	volatile uint32_t RSVD_3019;	 // 0x2f74 Reserved 3019.
	volatile uint32_t RSVD_3020;	 // 0x2f78 Reserved 3020.
	volatile uint32_t RSVD_3021;	 // 0x2f7c Reserved 3021.
	volatile uint32_t RSVD_3022;	 // 0x2f80 Reserved 3022.
	volatile uint32_t RSVD_3023;	 // 0x2f84 Reserved 3023.
	volatile uint32_t RSVD_3024;	 // 0x2f88 Reserved 3024.
	volatile uint32_t RSVD_3025;	 // 0x2f8c Reserved 3025.
	volatile uint32_t RSVD_3026;	 // 0x2f90 Reserved 3026.
	volatile uint32_t RSVD_3027;	 // 0x2f94 Reserved 3027.
	volatile uint32_t RSVD_3028;	 // 0x2f98 Reserved 3028.
	volatile uint32_t RSVD_3029;	 // 0x2f9c Reserved 3029.
	volatile uint32_t RSVD_3030;	 // 0x2fa0 Reserved 3030.
	volatile uint32_t RSVD_3031;	 // 0x2fa4 Reserved 3031.
	volatile uint32_t RSVD_3032;	 // 0x2fa8 Reserved 3032.
	volatile uint32_t RSVD_3033;	 // 0x2fac Reserved 3033.
	volatile uint32_t RSVD_3034;	 // 0x2fb0 Reserved 3034.
	volatile uint32_t RSVD_3035;	 // 0x2fb4 Reserved 3035.
	volatile uint32_t RSVD_3036;	 // 0x2fb8 Reserved 3036.
	volatile uint32_t RSVD_3037;	 // 0x2fbc Reserved 3037.
	volatile uint32_t RSVD_3038;	 // 0x2fc0 Reserved 3038.
	volatile uint32_t RSVD_3039;	 // 0x2fc4 Reserved 3039.
	volatile uint32_t RSVD_3040;	 // 0x2fc8 Reserved 3040.
	volatile uint32_t RSVD_3041;	 // 0x2fcc Reserved 3041.
	volatile uint32_t RSVD_3042;	 // 0x2fd0 Reserved 3042.
	volatile uint32_t RSVD_3043;	 // 0x2fd4 Reserved 3043.
	volatile uint32_t RSVD_3044;	 // 0x2fd8 Reserved 3044.
	volatile uint32_t RSVD_3045;	 // 0x2fdc Reserved 3045.
	volatile uint32_t RSVD_3046;	 // 0x2fe0 Reserved 3046.
	volatile uint32_t RSVD_3047;	 // 0x2fe4 Reserved 3047.
	volatile uint32_t RSVD_3048;	 // 0x2fe8 Reserved 3048.
	volatile uint32_t RSVD_3049;	 // 0x2fec Reserved 3049.
	volatile uint32_t RSVD_3050;	 // 0x2ff0 Reserved 3050.
	volatile uint32_t RSVD_3051;	 // 0x2ff4 Reserved 3051.
	volatile uint32_t RSVD_3052;	 // 0x2ff8 Reserved 3052.
	volatile uint32_t RSVD_3053;	 // 0x2ffc Reserved 3053.
	volatile uint32_t RSVD_3054;	 // 0x3000 Reserved 3054.
	volatile uint32_t RSVD_3055;	 // 0x3004 Reserved 3055.
	volatile uint32_t RSVD_3056;	 // 0x3008 Reserved 3056.
	volatile uint32_t RSVD_3057;	 // 0x300c Reserved 3057.
	volatile uint32_t RSVD_3058;	 // 0x3010 Reserved 3058.
	volatile uint32_t RSVD_3059;	 // 0x3014 Reserved 3059.
	volatile uint32_t RSVD_3060;	 // 0x3018 Reserved 3060.
	volatile uint32_t RSVD_3061;	 // 0x301c Reserved 3061.
	volatile uint32_t RSVD_3062;	 // 0x3020 Reserved 3062.
	volatile uint32_t RSVD_3063;	 // 0x3024 Reserved 3063.
	volatile uint32_t RSVD_3064;	 // 0x3028 Reserved 3064.
	volatile uint32_t RSVD_3065;	 // 0x302c Reserved 3065.
	volatile uint32_t RSVD_3066;	 // 0x3030 Reserved 3066.
	volatile uint32_t RSVD_3067;	 // 0x3034 Reserved 3067.
	volatile uint32_t RSVD_3068;	 // 0x3038 Reserved 3068.
	volatile uint32_t RSVD_3069;	 // 0x303c Reserved 3069.
	volatile uint32_t RSVD_3070;	 // 0x3040 Reserved 3070.
	volatile uint32_t RSVD_3071;	 // 0x3044 Reserved 3071.
	volatile uint32_t RSVD_3072;	 // 0x3048 Reserved 3072.
	volatile uint32_t RSVD_3073;	 // 0x304c Reserved 3073.
	volatile uint32_t RSVD_3074;	 // 0x3050 Reserved 3074.
	volatile uint32_t RSVD_3075;	 // 0x3054 Reserved 3075.
	volatile uint32_t RSVD_3076;	 // 0x3058 Reserved 3076.
	volatile uint32_t RSVD_3077;	 // 0x305c Reserved 3077.
	volatile uint32_t RSVD_3078;	 // 0x3060 Reserved 3078.
	volatile uint32_t RSVD_3079;	 // 0x3064 Reserved 3079.
	volatile uint32_t RSVD_3080;	 // 0x3068 Reserved 3080.
	volatile uint32_t RSVD_3081;	 // 0x306c Reserved 3081.
	volatile uint32_t RSVD_3082;	 // 0x3070 Reserved 3082.
	volatile uint32_t RSVD_3083;	 // 0x3074 Reserved 3083.
	volatile uint32_t RSVD_3084;	 // 0x3078 Reserved 3084.
	volatile uint32_t RSVD_3085;	 // 0x307c Reserved 3085.
	volatile uint32_t RSVD_3086;	 // 0x3080 Reserved 3086.
	volatile uint32_t RSVD_3087;	 // 0x3084 Reserved 3087.
	volatile uint32_t RSVD_3088;	 // 0x3088 Reserved 3088.
	volatile uint32_t RSVD_3089;	 // 0x308c Reserved 3089.
	volatile uint32_t RSVD_3090;	 // 0x3090 Reserved 3090.
	volatile uint32_t RSVD_3091;	 // 0x3094 Reserved 3091.
	volatile uint32_t RSVD_3092;	 // 0x3098 Reserved 3092.
	volatile uint32_t RSVD_3093;	 // 0x309c Reserved 3093.
	volatile uint32_t RSVD_3094;	 // 0x30a0 Reserved 3094.
	volatile uint32_t RSVD_3095;	 // 0x30a4 Reserved 3095.
	volatile uint32_t RSVD_3096;	 // 0x30a8 Reserved 3096.
	volatile uint32_t RSVD_3097;	 // 0x30ac Reserved 3097.
	volatile uint32_t RSVD_3098;	 // 0x30b0 Reserved 3098.
	volatile uint32_t RSVD_3099;	 // 0x30b4 Reserved 3099.
	volatile uint32_t RSVD_3100;	 // 0x30b8 Reserved 3100.
	volatile uint32_t RSVD_3101;	 // 0x30bc Reserved 3101.
	volatile uint32_t RSVD_3102;	 // 0x30c0 Reserved 3102.
	volatile uint32_t RSVD_3103;	 // 0x30c4 Reserved 3103.
	volatile uint32_t RSVD_3104;	 // 0x30c8 Reserved 3104.
	volatile uint32_t RSVD_3105;	 // 0x30cc Reserved 3105.
	volatile uint32_t RSVD_3106;	 // 0x30d0 Reserved 3106.
	volatile uint32_t RSVD_3107;	 // 0x30d4 Reserved 3107.
	volatile uint32_t RSVD_3108;	 // 0x30d8 Reserved 3108.
	volatile uint32_t RSVD_3109;	 // 0x30dc Reserved 3109.
	volatile uint32_t RSVD_3110;	 // 0x30e0 Reserved 3110.
	volatile uint32_t RSVD_3111;	 // 0x30e4 Reserved 3111.
	volatile uint32_t RSVD_3112;	 // 0x30e8 Reserved 3112.
	volatile uint32_t RSVD_3113;	 // 0x30ec Reserved 3113.
	volatile uint32_t RSVD_3114;	 // 0x30f0 Reserved 3114.
	volatile uint32_t RSVD_3115;	 // 0x30f4 Reserved 3115.
	volatile uint32_t RSVD_3116;	 // 0x30f8 Reserved 3116.
	volatile uint32_t RSVD_3117;	 // 0x30fc Reserved 3117.
	volatile uint32_t RSVD_3118;	 // 0x3100 Reserved 3118.
	volatile uint32_t RSVD_3119;	 // 0x3104 Reserved 3119.
	volatile uint32_t RSVD_3120;	 // 0x3108 Reserved 3120.
	volatile uint32_t RSVD_3121;	 // 0x310c Reserved 3121.
	volatile uint32_t RSVD_3122;	 // 0x3110 Reserved 3122.
	volatile uint32_t RSVD_3123;	 // 0x3114 Reserved 3123.
	volatile uint32_t RSVD_3124;	 // 0x3118 Reserved 3124.
	volatile uint32_t RSVD_3125;	 // 0x311c Reserved 3125.
	volatile uint32_t RSVD_3126;	 // 0x3120 Reserved 3126.
	volatile uint32_t RSVD_3127;	 // 0x3124 Reserved 3127.
	volatile uint32_t RSVD_3128;	 // 0x3128 Reserved 3128.
	volatile uint32_t RSVD_3129;	 // 0x312c Reserved 3129.
	volatile uint32_t RSVD_3130;	 // 0x3130 Reserved 3130.
	volatile uint32_t RSVD_3131;	 // 0x3134 Reserved 3131.
	volatile uint32_t RSVD_3132;	 // 0x3138 Reserved 3132.
	volatile uint32_t RSVD_3133;	 // 0x313c Reserved 3133.
	volatile uint32_t RSVD_3134;	 // 0x3140 Reserved 3134.
	volatile uint32_t RSVD_3135;	 // 0x3144 Reserved 3135.
	volatile uint32_t RSVD_3136;	 // 0x3148 Reserved 3136.
	volatile uint32_t RSVD_3137;	 // 0x314c Reserved 3137.
	volatile uint32_t RSVD_3138;	 // 0x3150 Reserved 3138.
	volatile uint32_t RSVD_3139;	 // 0x3154 Reserved 3139.
	volatile uint32_t RSVD_3140;	 // 0x3158 Reserved 3140.
	volatile uint32_t RSVD_3141;	 // 0x315c Reserved 3141.
	volatile uint32_t RSVD_3142;	 // 0x3160 Reserved 3142.
	volatile uint32_t RSVD_3143;	 // 0x3164 Reserved 3143.
	volatile uint32_t RSVD_3144;	 // 0x3168 Reserved 3144.
	volatile uint32_t RSVD_3145;	 // 0x316c Reserved 3145.
	volatile uint32_t RSVD_3146;	 // 0x3170 Reserved 3146.
	volatile uint32_t RSVD_3147;	 // 0x3174 Reserved 3147.
	volatile uint32_t RSVD_3148;	 // 0x3178 Reserved 3148.
	volatile uint32_t RSVD_3149;	 // 0x317c Reserved 3149.
	volatile uint32_t RSVD_3150;	 // 0x3180 Reserved 3150.
	volatile uint32_t RSVD_3151;	 // 0x3184 Reserved 3151.
	volatile uint32_t RSVD_3152;	 // 0x3188 Reserved 3152.
	volatile uint32_t RSVD_3153;	 // 0x318c Reserved 3153.
	volatile uint32_t RSVD_3154;	 // 0x3190 Reserved 3154.
	volatile uint32_t RSVD_3155;	 // 0x3194 Reserved 3155.
	volatile uint32_t RSVD_3156;	 // 0x3198 Reserved 3156.
	volatile uint32_t RSVD_3157;	 // 0x319c Reserved 3157.
	volatile uint32_t RSVD_3158;	 // 0x31a0 Reserved 3158.
	volatile uint32_t RSVD_3159;	 // 0x31a4 Reserved 3159.
	volatile uint32_t RSVD_3160;	 // 0x31a8 Reserved 3160.
	volatile uint32_t RSVD_3161;	 // 0x31ac Reserved 3161.
	volatile uint32_t RSVD_3162;	 // 0x31b0 Reserved 3162.
	volatile uint32_t RSVD_3163;	 // 0x31b4 Reserved 3163.
	volatile uint32_t RSVD_3164;	 // 0x31b8 Reserved 3164.
	volatile uint32_t RSVD_3165;	 // 0x31bc Reserved 3165.
	volatile uint32_t RSVD_3166;	 // 0x31c0 Reserved 3166.
	volatile uint32_t RSVD_3167;	 // 0x31c4 Reserved 3167.
	volatile uint32_t RSVD_3168;	 // 0x31c8 Reserved 3168.
	volatile uint32_t RSVD_3169;	 // 0x31cc Reserved 3169.
	volatile uint32_t RSVD_3170;	 // 0x31d0 Reserved 3170.
	volatile uint32_t RSVD_3171;	 // 0x31d4 Reserved 3171.
	volatile uint32_t RSVD_3172;	 // 0x31d8 Reserved 3172.
	volatile uint32_t RSVD_3173;	 // 0x31dc Reserved 3173.
	volatile uint32_t RSVD_3174;	 // 0x31e0 Reserved 3174.
	volatile uint32_t RSVD_3175;	 // 0x31e4 Reserved 3175.
	volatile uint32_t RSVD_3176;	 // 0x31e8 Reserved 3176.
	volatile uint32_t RSVD_3177;	 // 0x31ec Reserved 3177.
	volatile uint32_t RSVD_3178;	 // 0x31f0 Reserved 3178.
	volatile uint32_t RSVD_3179;	 // 0x31f4 Reserved 3179.
	volatile uint32_t RSVD_3180;	 // 0x31f8 Reserved 3180.
	volatile uint32_t RSVD_3181;	 // 0x31fc Reserved 3181.
	volatile uint32_t RSVD_3182;	 // 0x3200 Reserved 3182.
	volatile uint32_t RSVD_3183;	 // 0x3204 Reserved 3183.
	volatile uint32_t RSVD_3184;	 // 0x3208 Reserved 3184.
	volatile uint32_t RSVD_3185;	 // 0x320c Reserved 3185.
	volatile uint32_t RSVD_3186;	 // 0x3210 Reserved 3186.
	volatile uint32_t RSVD_3187;	 // 0x3214 Reserved 3187.
	volatile uint32_t RSVD_3188;	 // 0x3218 Reserved 3188.
	volatile uint32_t RSVD_3189;	 // 0x321c Reserved 3189.
	volatile uint32_t RSVD_3190;	 // 0x3220 Reserved 3190.
	volatile uint32_t RSVD_3191;	 // 0x3224 Reserved 3191.
	volatile uint32_t RSVD_3192;	 // 0x3228 Reserved 3192.
	volatile uint32_t RSVD_3193;	 // 0x322c Reserved 3193.
	volatile uint32_t RSVD_3194;	 // 0x3230 Reserved 3194.
	volatile uint32_t RSVD_3195;	 // 0x3234 Reserved 3195.
	volatile uint32_t RSVD_3196;	 // 0x3238 Reserved 3196.
	volatile uint32_t RSVD_3197;	 // 0x323c Reserved 3197.
	volatile uint32_t RSVD_3198;	 // 0x3240 Reserved 3198.
	volatile uint32_t RSVD_3199;	 // 0x3244 Reserved 3199.
	volatile uint32_t RSVD_3200;	 // 0x3248 Reserved 3200.
	volatile uint32_t RSVD_3201;	 // 0x324c Reserved 3201.
	volatile uint32_t RSVD_3202;	 // 0x3250 Reserved 3202.
	volatile uint32_t RSVD_3203;	 // 0x3254 Reserved 3203.
	volatile uint32_t RSVD_3204;	 // 0x3258 Reserved 3204.
	volatile uint32_t RSVD_3205;	 // 0x325c Reserved 3205.
	volatile uint32_t RSVD_3206;	 // 0x3260 Reserved 3206.
	volatile uint32_t RSVD_3207;	 // 0x3264 Reserved 3207.
	volatile uint32_t RSVD_3208;	 // 0x3268 Reserved 3208.
	volatile uint32_t RSVD_3209;	 // 0x326c Reserved 3209.
	volatile uint32_t RSVD_3210;	 // 0x3270 Reserved 3210.
	volatile uint32_t RSVD_3211;	 // 0x3274 Reserved 3211.
	volatile uint32_t RSVD_3212;	 // 0x3278 Reserved 3212.
	volatile uint32_t RSVD_3213;	 // 0x327c Reserved 3213.
	volatile uint32_t RSVD_3214;	 // 0x3280 Reserved 3214.
	volatile uint32_t RSVD_3215;	 // 0x3284 Reserved 3215.
	volatile uint32_t RSVD_3216;	 // 0x3288 Reserved 3216.
	volatile uint32_t RSVD_3217;	 // 0x328c Reserved 3217.
	volatile uint32_t RSVD_3218;	 // 0x3290 Reserved 3218.
	volatile uint32_t RSVD_3219;	 // 0x3294 Reserved 3219.
	volatile uint32_t RSVD_3220;	 // 0x3298 Reserved 3220.
	volatile uint32_t RSVD_3221;	 // 0x329c Reserved 3221.
	volatile uint32_t RSVD_3222;	 // 0x32a0 Reserved 3222.
	volatile uint32_t RSVD_3223;	 // 0x32a4 Reserved 3223.
	volatile uint32_t RSVD_3224;	 // 0x32a8 Reserved 3224.
	volatile uint32_t RSVD_3225;	 // 0x32ac Reserved 3225.
	volatile uint32_t RSVD_3226;	 // 0x32b0 Reserved 3226.
	volatile uint32_t RSVD_3227;	 // 0x32b4 Reserved 3227.
	volatile uint32_t RSVD_3228;	 // 0x32b8 Reserved 3228.
	volatile uint32_t RSVD_3229;	 // 0x32bc Reserved 3229.
	volatile uint32_t RSVD_3230;	 // 0x32c0 Reserved 3230.
	volatile uint32_t RSVD_3231;	 // 0x32c4 Reserved 3231.
	volatile uint32_t RSVD_3232;	 // 0x32c8 Reserved 3232.
	volatile uint32_t RSVD_3233;	 // 0x32cc Reserved 3233.
	volatile uint32_t RSVD_3234;	 // 0x32d0 Reserved 3234.
	volatile uint32_t RSVD_3235;	 // 0x32d4 Reserved 3235.
	volatile uint32_t RSVD_3236;	 // 0x32d8 Reserved 3236.
	volatile uint32_t RSVD_3237;	 // 0x32dc Reserved 3237.
	volatile uint32_t RSVD_3238;	 // 0x32e0 Reserved 3238.
	volatile uint32_t RSVD_3239;	 // 0x32e4 Reserved 3239.
	volatile uint32_t RSVD_3240;	 // 0x32e8 Reserved 3240.
	volatile uint32_t RSVD_3241;	 // 0x32ec Reserved 3241.
	volatile uint32_t RSVD_3242;	 // 0x32f0 Reserved 3242.
	volatile uint32_t RSVD_3243;	 // 0x32f4 Reserved 3243.
	volatile uint32_t RSVD_3244;	 // 0x32f8 Reserved 3244.
	volatile uint32_t RSVD_3245;	 // 0x32fc Reserved 3245.
	volatile uint32_t RSVD_3246;	 // 0x3300 Reserved 3246.
	volatile uint32_t RSVD_3247;	 // 0x3304 Reserved 3247.
	volatile uint32_t RSVD_3248;	 // 0x3308 Reserved 3248.
	volatile uint32_t RSVD_3249;	 // 0x330c Reserved 3249.
	volatile uint32_t RSVD_3250;	 // 0x3310 Reserved 3250.
	volatile uint32_t RSVD_3251;	 // 0x3314 Reserved 3251.
	volatile uint32_t RSVD_3252;	 // 0x3318 Reserved 3252.
	volatile uint32_t RSVD_3253;	 // 0x331c Reserved 3253.
	volatile uint32_t RSVD_3254;	 // 0x3320 Reserved 3254.
	volatile uint32_t RSVD_3255;	 // 0x3324 Reserved 3255.
	volatile uint32_t RSVD_3256;	 // 0x3328 Reserved 3256.
	volatile uint32_t RSVD_3257;	 // 0x332c Reserved 3257.
	volatile uint32_t RSVD_3258;	 // 0x3330 Reserved 3258.
	volatile uint32_t RSVD_3259;	 // 0x3334 Reserved 3259.
	volatile uint32_t RSVD_3260;	 // 0x3338 Reserved 3260.
	volatile uint32_t RSVD_3261;	 // 0x333c Reserved 3261.
	volatile uint32_t RSVD_3262;	 // 0x3340 Reserved 3262.
	volatile uint32_t RSVD_3263;	 // 0x3344 Reserved 3263.
	volatile uint32_t RSVD_3264;	 // 0x3348 Reserved 3264.
	volatile uint32_t RSVD_3265;	 // 0x334c Reserved 3265.
	volatile uint32_t RSVD_3266;	 // 0x3350 Reserved 3266.
	volatile uint32_t RSVD_3267;	 // 0x3354 Reserved 3267.
	volatile uint32_t RSVD_3268;	 // 0x3358 Reserved 3268.
	volatile uint32_t RSVD_3269;	 // 0x335c Reserved 3269.
	volatile uint32_t RSVD_3270;	 // 0x3360 Reserved 3270.
	volatile uint32_t RSVD_3271;	 // 0x3364 Reserved 3271.
	volatile uint32_t RSVD_3272;	 // 0x3368 Reserved 3272.
	volatile uint32_t RSVD_3273;	 // 0x336c Reserved 3273.
	volatile uint32_t RSVD_3274;	 // 0x3370 Reserved 3274.
	volatile uint32_t RSVD_3275;	 // 0x3374 Reserved 3275.
	volatile uint32_t RSVD_3276;	 // 0x3378 Reserved 3276.
	volatile uint32_t RSVD_3277;	 // 0x337c Reserved 3277.
	volatile uint32_t RSVD_3278;	 // 0x3380 Reserved 3278.
	volatile uint32_t RSVD_3279;	 // 0x3384 Reserved 3279.
	volatile uint32_t RSVD_3280;	 // 0x3388 Reserved 3280.
	volatile uint32_t RSVD_3281;	 // 0x338c Reserved 3281.
	volatile uint32_t RSVD_3282;	 // 0x3390 Reserved 3282.
	volatile uint32_t RSVD_3283;	 // 0x3394 Reserved 3283.
	volatile uint32_t RSVD_3284;	 // 0x3398 Reserved 3284.
	volatile uint32_t RSVD_3285;	 // 0x339c Reserved 3285.
	volatile uint32_t RSVD_3286;	 // 0x33a0 Reserved 3286.
	volatile uint32_t RSVD_3287;	 // 0x33a4 Reserved 3287.
	volatile uint32_t RSVD_3288;	 // 0x33a8 Reserved 3288.
	volatile uint32_t RSVD_3289;	 // 0x33ac Reserved 3289.
	volatile uint32_t RSVD_3290;	 // 0x33b0 Reserved 3290.
	volatile uint32_t RSVD_3291;	 // 0x33b4 Reserved 3291.
	volatile uint32_t RSVD_3292;	 // 0x33b8 Reserved 3292.
	volatile uint32_t RSVD_3293;	 // 0x33bc Reserved 3293.
	volatile uint32_t RSVD_3294;	 // 0x33c0 Reserved 3294.
	volatile uint32_t RSVD_3295;	 // 0x33c4 Reserved 3295.
	volatile uint32_t RSVD_3296;	 // 0x33c8 Reserved 3296.
	volatile uint32_t RSVD_3297;	 // 0x33cc Reserved 3297.
	volatile uint32_t RSVD_3298;	 // 0x33d0 Reserved 3298.
	volatile uint32_t RSVD_3299;	 // 0x33d4 Reserved 3299.
	volatile uint32_t RSVD_3300;	 // 0x33d8 Reserved 3300.
	volatile uint32_t RSVD_3301;	 // 0x33dc Reserved 3301.
	volatile uint32_t RSVD_3302;	 // 0x33e0 Reserved 3302.
	volatile uint32_t RSVD_3303;	 // 0x33e4 Reserved 3303.
	volatile uint32_t RSVD_3304;	 // 0x33e8 Reserved 3304.
	volatile uint32_t RSVD_3305;	 // 0x33ec Reserved 3305.
	volatile uint32_t RSVD_3306;	 // 0x33f0 Reserved 3306.
	volatile uint32_t RSVD_3307;	 // 0x33f4 Reserved 3307.
	volatile uint32_t RSVD_3308;	 // 0x33f8 Reserved 3308.
	volatile uint32_t RSVD_3309;	 // 0x33fc Reserved 3309.
	volatile uint32_t RSVD_3310;	 // 0x3400 Reserved 3310.
	volatile uint32_t RSVD_3311;	 // 0x3404 Reserved 3311.
	volatile uint32_t RSVD_3312;	 // 0x3408 Reserved 3312.
	volatile uint32_t RSVD_3313;	 // 0x340c Reserved 3313.
	volatile uint32_t RSVD_3314;	 // 0x3410 Reserved 3314.
	volatile uint32_t RSVD_3315;	 // 0x3414 Reserved 3315.
	volatile uint32_t RSVD_3316;	 // 0x3418 Reserved 3316.
	volatile uint32_t RSVD_3317;	 // 0x341c Reserved 3317.
	volatile uint32_t RSVD_3318;	 // 0x3420 Reserved 3318.
	volatile uint32_t RSVD_3319;	 // 0x3424 Reserved 3319.
	volatile uint32_t RSVD_3320;	 // 0x3428 Reserved 3320.
	volatile uint32_t RSVD_3321;	 // 0x342c Reserved 3321.
	volatile uint32_t RSVD_3322;	 // 0x3430 Reserved 3322.
	volatile uint32_t RSVD_3323;	 // 0x3434 Reserved 3323.
	volatile uint32_t RSVD_3324;	 // 0x3438 Reserved 3324.
	volatile uint32_t RSVD_3325;	 // 0x343c Reserved 3325.
	volatile uint32_t RSVD_3326;	 // 0x3440 Reserved 3326.
	volatile uint32_t RSVD_3327;	 // 0x3444 Reserved 3327.
	volatile uint32_t RSVD_3328;	 // 0x3448 Reserved 3328.
	volatile uint32_t RSVD_3329;	 // 0x344c Reserved 3329.
	volatile uint32_t RSVD_3330;	 // 0x3450 Reserved 3330.
	volatile uint32_t RSVD_3331;	 // 0x3454 Reserved 3331.
	volatile uint32_t RSVD_3332;	 // 0x3458 Reserved 3332.
	volatile uint32_t RSVD_3333;	 // 0x345c Reserved 3333.
	volatile uint32_t RSVD_3334;	 // 0x3460 Reserved 3334.
	volatile uint32_t RSVD_3335;	 // 0x3464 Reserved 3335.
	volatile uint32_t RSVD_3336;	 // 0x3468 Reserved 3336.
	volatile uint32_t RSVD_3337;	 // 0x346c Reserved 3337.
	volatile uint32_t RSVD_3338;	 // 0x3470 Reserved 3338.
	volatile uint32_t RSVD_3339;	 // 0x3474 Reserved 3339.
	volatile uint32_t RSVD_3340;	 // 0x3478 Reserved 3340.
	volatile uint32_t RSVD_3341;	 // 0x347c Reserved 3341.
	volatile uint32_t RSVD_3342;	 // 0x3480 Reserved 3342.
	volatile uint32_t RSVD_3343;	 // 0x3484 Reserved 3343.
	volatile uint32_t RSVD_3344;	 // 0x3488 Reserved 3344.
	volatile uint32_t RSVD_3345;	 // 0x348c Reserved 3345.
	volatile uint32_t RSVD_3346;	 // 0x3490 Reserved 3346.
	volatile uint32_t RSVD_3347;	 // 0x3494 Reserved 3347.
	volatile uint32_t RSVD_3348;	 // 0x3498 Reserved 3348.
	volatile uint32_t RSVD_3349;	 // 0x349c Reserved 3349.
	volatile uint32_t RSVD_3350;	 // 0x34a0 Reserved 3350.
	volatile uint32_t RSVD_3351;	 // 0x34a4 Reserved 3351.
	volatile uint32_t RSVD_3352;	 // 0x34a8 Reserved 3352.
	volatile uint32_t RSVD_3353;	 // 0x34ac Reserved 3353.
	volatile uint32_t RSVD_3354;	 // 0x34b0 Reserved 3354.
	volatile uint32_t RSVD_3355;	 // 0x34b4 Reserved 3355.
	volatile uint32_t RSVD_3356;	 // 0x34b8 Reserved 3356.
	volatile uint32_t RSVD_3357;	 // 0x34bc Reserved 3357.
	volatile uint32_t RSVD_3358;	 // 0x34c0 Reserved 3358.
	volatile uint32_t RSVD_3359;	 // 0x34c4 Reserved 3359.
	volatile uint32_t RSVD_3360;	 // 0x34c8 Reserved 3360.
	volatile uint32_t RSVD_3361;	 // 0x34cc Reserved 3361.
	volatile uint32_t RSVD_3362;	 // 0x34d0 Reserved 3362.
	volatile uint32_t RSVD_3363;	 // 0x34d4 Reserved 3363.
	volatile uint32_t RSVD_3364;	 // 0x34d8 Reserved 3364.
	volatile uint32_t RSVD_3365;	 // 0x34dc Reserved 3365.
	volatile uint32_t RSVD_3366;	 // 0x34e0 Reserved 3366.
	volatile uint32_t RSVD_3367;	 // 0x34e4 Reserved 3367.
	volatile uint32_t RSVD_3368;	 // 0x34e8 Reserved 3368.
	volatile uint32_t RSVD_3369;	 // 0x34ec Reserved 3369.
	volatile uint32_t RSVD_3370;	 // 0x34f0 Reserved 3370.
	volatile uint32_t RSVD_3371;	 // 0x34f4 Reserved 3371.
	volatile uint32_t RSVD_3372;	 // 0x34f8 Reserved 3372.
	volatile uint32_t RSVD_3373;	 // 0x34fc Reserved 3373.
	volatile uint32_t RSVD_3374;	 // 0x3500 Reserved 3374.
	volatile uint32_t RSVD_3375;	 // 0x3504 Reserved 3375.
	volatile uint32_t RSVD_3376;	 // 0x3508 Reserved 3376.
	volatile uint32_t RSVD_3377;	 // 0x350c Reserved 3377.
	volatile uint32_t RSVD_3378;	 // 0x3510 Reserved 3378.
	volatile uint32_t RSVD_3379;	 // 0x3514 Reserved 3379.
	volatile uint32_t RSVD_3380;	 // 0x3518 Reserved 3380.
	volatile uint32_t RSVD_3381;	 // 0x351c Reserved 3381.
	volatile uint32_t RSVD_3382;	 // 0x3520 Reserved 3382.
	volatile uint32_t RSVD_3383;	 // 0x3524 Reserved 3383.
	volatile uint32_t RSVD_3384;	 // 0x3528 Reserved 3384.
	volatile uint32_t RSVD_3385;	 // 0x352c Reserved 3385.
	volatile uint32_t RSVD_3386;	 // 0x3530 Reserved 3386.
	volatile uint32_t RSVD_3387;	 // 0x3534 Reserved 3387.
	volatile uint32_t RSVD_3388;	 // 0x3538 Reserved 3388.
	volatile uint32_t RSVD_3389;	 // 0x353c Reserved 3389.
	volatile uint32_t RSVD_3390;	 // 0x3540 Reserved 3390.
	volatile uint32_t RSVD_3391;	 // 0x3544 Reserved 3391.
	volatile uint32_t RSVD_3392;	 // 0x3548 Reserved 3392.
	volatile uint32_t RSVD_3393;	 // 0x354c Reserved 3393.
	volatile uint32_t RSVD_3394;	 // 0x3550 Reserved 3394.
	volatile uint32_t RSVD_3395;	 // 0x3554 Reserved 3395.
	volatile uint32_t RSVD_3396;	 // 0x3558 Reserved 3396.
	volatile uint32_t RSVD_3397;	 // 0x355c Reserved 3397.
	volatile uint32_t RSVD_3398;	 // 0x3560 Reserved 3398.
	volatile uint32_t RSVD_3399;	 // 0x3564 Reserved 3399.
	volatile uint32_t RSVD_3400;	 // 0x3568 Reserved 3400.
	volatile uint32_t RSVD_3401;	 // 0x356c Reserved 3401.
	volatile uint32_t RSVD_3402;	 // 0x3570 Reserved 3402.
	volatile uint32_t RSVD_3403;	 // 0x3574 Reserved 3403.
	volatile uint32_t RSVD_3404;	 // 0x3578 Reserved 3404.
	volatile uint32_t RSVD_3405;	 // 0x357c Reserved 3405.
	volatile uint32_t RSVD_3406;	 // 0x3580 Reserved 3406.
	volatile uint32_t RSVD_3407;	 // 0x3584 Reserved 3407.
	volatile uint32_t RSVD_3408;	 // 0x3588 Reserved 3408.
	volatile uint32_t RSVD_3409;	 // 0x358c Reserved 3409.
	volatile uint32_t RSVD_3410;	 // 0x3590 Reserved 3410.
	volatile uint32_t RSVD_3411;	 // 0x3594 Reserved 3411.
	volatile uint32_t RSVD_3412;	 // 0x3598 Reserved 3412.
	volatile uint32_t RSVD_3413;	 // 0x359c Reserved 3413.
	volatile uint32_t RSVD_3414;	 // 0x35a0 Reserved 3414.
	volatile uint32_t RSVD_3415;	 // 0x35a4 Reserved 3415.
	volatile uint32_t RSVD_3416;	 // 0x35a8 Reserved 3416.
	volatile uint32_t RSVD_3417;	 // 0x35ac Reserved 3417.
	volatile uint32_t RSVD_3418;	 // 0x35b0 Reserved 3418.
	volatile uint32_t RSVD_3419;	 // 0x35b4 Reserved 3419.
	volatile uint32_t RSVD_3420;	 // 0x35b8 Reserved 3420.
	volatile uint32_t RSVD_3421;	 // 0x35bc Reserved 3421.
	volatile uint32_t RSVD_3422;	 // 0x35c0 Reserved 3422.
	volatile uint32_t RSVD_3423;	 // 0x35c4 Reserved 3423.
	volatile uint32_t RSVD_3424;	 // 0x35c8 Reserved 3424.
	volatile uint32_t RSVD_3425;	 // 0x35cc Reserved 3425.
	volatile uint32_t RSVD_3426;	 // 0x35d0 Reserved 3426.
	volatile uint32_t RSVD_3427;	 // 0x35d4 Reserved 3427.
	volatile uint32_t RSVD_3428;	 // 0x35d8 Reserved 3428.
	volatile uint32_t RSVD_3429;	 // 0x35dc Reserved 3429.
	volatile uint32_t RSVD_3430;	 // 0x35e0 Reserved 3430.
	volatile uint32_t RSVD_3431;	 // 0x35e4 Reserved 3431.
	volatile uint32_t RSVD_3432;	 // 0x35e8 Reserved 3432.
	volatile uint32_t RSVD_3433;	 // 0x35ec Reserved 3433.
	volatile uint32_t RSVD_3434;	 // 0x35f0 Reserved 3434.
	volatile uint32_t RSVD_3435;	 // 0x35f4 Reserved 3435.
	volatile uint32_t RSVD_3436;	 // 0x35f8 Reserved 3436.
	volatile uint32_t RSVD_3437;	 // 0x35fc Reserved 3437.
	volatile uint32_t RSVD_3438;	 // 0x3600 Reserved 3438.
	volatile uint32_t RSVD_3439;	 // 0x3604 Reserved 3439.
	volatile uint32_t RSVD_3440;	 // 0x3608 Reserved 3440.
	volatile uint32_t RSVD_3441;	 // 0x360c Reserved 3441.
	volatile uint32_t RSVD_3442;	 // 0x3610 Reserved 3442.
	volatile uint32_t RSVD_3443;	 // 0x3614 Reserved 3443.
	volatile uint32_t RSVD_3444;	 // 0x3618 Reserved 3444.
	volatile uint32_t RSVD_3445;	 // 0x361c Reserved 3445.
	volatile uint32_t RSVD_3446;	 // 0x3620 Reserved 3446.
	volatile uint32_t RSVD_3447;	 // 0x3624 Reserved 3447.
	volatile uint32_t RSVD_3448;	 // 0x3628 Reserved 3448.
	volatile uint32_t RSVD_3449;	 // 0x362c Reserved 3449.
	volatile uint32_t RSVD_3450;	 // 0x3630 Reserved 3450.
	volatile uint32_t RSVD_3451;	 // 0x3634 Reserved 3451.
	volatile uint32_t RSVD_3452;	 // 0x3638 Reserved 3452.
	volatile uint32_t RSVD_3453;	 // 0x363c Reserved 3453.
	volatile uint32_t RSVD_3454;	 // 0x3640 Reserved 3454.
	volatile uint32_t RSVD_3455;	 // 0x3644 Reserved 3455.
	volatile uint32_t RSVD_3456;	 // 0x3648 Reserved 3456.
	volatile uint32_t RSVD_3457;	 // 0x364c Reserved 3457.
	volatile uint32_t RSVD_3458;	 // 0x3650 Reserved 3458.
	volatile uint32_t RSVD_3459;	 // 0x3654 Reserved 3459.
	volatile uint32_t RSVD_3460;	 // 0x3658 Reserved 3460.
	volatile uint32_t RSVD_3461;	 // 0x365c Reserved 3461.
	volatile uint32_t RSVD_3462;	 // 0x3660 Reserved 3462.
	volatile uint32_t RSVD_3463;	 // 0x3664 Reserved 3463.
	volatile uint32_t RSVD_3464;	 // 0x3668 Reserved 3464.
	volatile uint32_t RSVD_3465;	 // 0x366c Reserved 3465.
	volatile uint32_t RSVD_3466;	 // 0x3670 Reserved 3466.
	volatile uint32_t RSVD_3467;	 // 0x3674 Reserved 3467.
	volatile uint32_t RSVD_3468;	 // 0x3678 Reserved 3468.
	volatile uint32_t RSVD_3469;	 // 0x367c Reserved 3469.
	volatile uint32_t RSVD_3470;	 // 0x3680 Reserved 3470.
	volatile uint32_t RSVD_3471;	 // 0x3684 Reserved 3471.
	volatile uint32_t RSVD_3472;	 // 0x3688 Reserved 3472.
	volatile uint32_t RSVD_3473;	 // 0x368c Reserved 3473.
	volatile uint32_t RSVD_3474;	 // 0x3690 Reserved 3474.
	volatile uint32_t RSVD_3475;	 // 0x3694 Reserved 3475.
	volatile uint32_t RSVD_3476;	 // 0x3698 Reserved 3476.
	volatile uint32_t RSVD_3477;	 // 0x369c Reserved 3477.
	volatile uint32_t RSVD_3478;	 // 0x36a0 Reserved 3478.
	volatile uint32_t RSVD_3479;	 // 0x36a4 Reserved 3479.
	volatile uint32_t RSVD_3480;	 // 0x36a8 Reserved 3480.
	volatile uint32_t RSVD_3481;	 // 0x36ac Reserved 3481.
	volatile uint32_t RSVD_3482;	 // 0x36b0 Reserved 3482.
	volatile uint32_t RSVD_3483;	 // 0x36b4 Reserved 3483.
	volatile uint32_t RSVD_3484;	 // 0x36b8 Reserved 3484.
	volatile uint32_t RSVD_3485;	 // 0x36bc Reserved 3485.
	volatile uint32_t RSVD_3486;	 // 0x36c0 Reserved 3486.
	volatile uint32_t RSVD_3487;	 // 0x36c4 Reserved 3487.
	volatile uint32_t RSVD_3488;	 // 0x36c8 Reserved 3488.
	volatile uint32_t RSVD_3489;	 // 0x36cc Reserved 3489.
	volatile uint32_t RSVD_3490;	 // 0x36d0 Reserved 3490.
	volatile uint32_t RSVD_3491;	 // 0x36d4 Reserved 3491.
	volatile uint32_t RSVD_3492;	 // 0x36d8 Reserved 3492.
	volatile uint32_t RSVD_3493;	 // 0x36dc Reserved 3493.
	volatile uint32_t RSVD_3494;	 // 0x36e0 Reserved 3494.
	volatile uint32_t RSVD_3495;	 // 0x36e4 Reserved 3495.
	volatile uint32_t RSVD_3496;	 // 0x36e8 Reserved 3496.
	volatile uint32_t RSVD_3497;	 // 0x36ec Reserved 3497.
	volatile uint32_t RSVD_3498;	 // 0x36f0 Reserved 3498.
	volatile uint32_t RSVD_3499;	 // 0x36f4 Reserved 3499.
	volatile uint32_t RSVD_3500;	 // 0x36f8 Reserved 3500.
	volatile uint32_t RSVD_3501;	 // 0x36fc Reserved 3501.
	volatile uint32_t RSVD_3502;	 // 0x3700 Reserved 3502.
	volatile uint32_t RSVD_3503;	 // 0x3704 Reserved 3503.
	volatile uint32_t RSVD_3504;	 // 0x3708 Reserved 3504.
	volatile uint32_t RSVD_3505;	 // 0x370c Reserved 3505.
	volatile uint32_t RSVD_3506;	 // 0x3710 Reserved 3506.
	volatile uint32_t RSVD_3507;	 // 0x3714 Reserved 3507.
	volatile uint32_t RSVD_3508;	 // 0x3718 Reserved 3508.
	volatile uint32_t RSVD_3509;	 // 0x371c Reserved 3509.
	volatile uint32_t RSVD_3510;	 // 0x3720 Reserved 3510.
	volatile uint32_t RSVD_3511;	 // 0x3724 Reserved 3511.
	volatile uint32_t RSVD_3512;	 // 0x3728 Reserved 3512.
	volatile uint32_t RSVD_3513;	 // 0x372c Reserved 3513.
	volatile uint32_t RSVD_3514;	 // 0x3730 Reserved 3514.
	volatile uint32_t RSVD_3515;	 // 0x3734 Reserved 3515.
	volatile uint32_t RSVD_3516;	 // 0x3738 Reserved 3516.
	volatile uint32_t RSVD_3517;	 // 0x373c Reserved 3517.
	volatile uint32_t RSVD_3518;	 // 0x3740 Reserved 3518.
	volatile uint32_t RSVD_3519;	 // 0x3744 Reserved 3519.
	volatile uint32_t RSVD_3520;	 // 0x3748 Reserved 3520.
	volatile uint32_t RSVD_3521;	 // 0x374c Reserved 3521.
	volatile uint32_t RSVD_3522;	 // 0x3750 Reserved 3522.
	volatile uint32_t RSVD_3523;	 // 0x3754 Reserved 3523.
	volatile uint32_t RSVD_3524;	 // 0x3758 Reserved 3524.
	volatile uint32_t RSVD_3525;	 // 0x375c Reserved 3525.
	volatile uint32_t RSVD_3526;	 // 0x3760 Reserved 3526.
	volatile uint32_t RSVD_3527;	 // 0x3764 Reserved 3527.
	volatile uint32_t RSVD_3528;	 // 0x3768 Reserved 3528.
	volatile uint32_t RSVD_3529;	 // 0x376c Reserved 3529.
	volatile uint32_t RSVD_3530;	 // 0x3770 Reserved 3530.
	volatile uint32_t RSVD_3531;	 // 0x3774 Reserved 3531.
	volatile uint32_t RSVD_3532;	 // 0x3778 Reserved 3532.
	volatile uint32_t RSVD_3533;	 // 0x377c Reserved 3533.
	volatile uint32_t RSVD_3534;	 // 0x3780 Reserved 3534.
	volatile uint32_t RSVD_3535;	 // 0x3784 Reserved 3535.
	volatile uint32_t RSVD_3536;	 // 0x3788 Reserved 3536.
	volatile uint32_t RSVD_3537;	 // 0x378c Reserved 3537.
	volatile uint32_t RSVD_3538;	 // 0x3790 Reserved 3538.
	volatile uint32_t RSVD_3539;	 // 0x3794 Reserved 3539.
	volatile uint32_t RSVD_3540;	 // 0x3798 Reserved 3540.
	volatile uint32_t RSVD_3541;	 // 0x379c Reserved 3541.
	volatile uint32_t RSVD_3542;	 // 0x37a0 Reserved 3542.
	volatile uint32_t RSVD_3543;	 // 0x37a4 Reserved 3543.
	volatile uint32_t RSVD_3544;	 // 0x37a8 Reserved 3544.
	volatile uint32_t RSVD_3545;	 // 0x37ac Reserved 3545.
	volatile uint32_t RSVD_3546;	 // 0x37b0 Reserved 3546.
	volatile uint32_t RSVD_3547;	 // 0x37b4 Reserved 3547.
	volatile uint32_t RSVD_3548;	 // 0x37b8 Reserved 3548.
	volatile uint32_t RSVD_3549;	 // 0x37bc Reserved 3549.
	volatile uint32_t RSVD_3550;	 // 0x37c0 Reserved 3550.
	volatile uint32_t RSVD_3551;	 // 0x37c4 Reserved 3551.
	volatile uint32_t RSVD_3552;	 // 0x37c8 Reserved 3552.
	volatile uint32_t RSVD_3553;	 // 0x37cc Reserved 3553.
	volatile uint32_t RSVD_3554;	 // 0x37d0 Reserved 3554.
	volatile uint32_t RSVD_3555;	 // 0x37d4 Reserved 3555.
	volatile uint32_t RSVD_3556;	 // 0x37d8 Reserved 3556.
	volatile uint32_t RSVD_3557;	 // 0x37dc Reserved 3557.
	volatile uint32_t RSVD_3558;	 // 0x37e0 Reserved 3558.
	volatile uint32_t RSVD_3559;	 // 0x37e4 Reserved 3559.
	volatile uint32_t RSVD_3560;	 // 0x37e8 Reserved 3560.
	volatile uint32_t RSVD_3561;	 // 0x37ec Reserved 3561.
	volatile uint32_t RSVD_3562;	 // 0x37f0 Reserved 3562.
	volatile uint32_t RSVD_3563;	 // 0x37f4 Reserved 3563.
	volatile uint32_t RSVD_3564;	 // 0x37f8 Reserved 3564.
	volatile uint32_t RSVD_3565;	 // 0x37fc Reserved 3565.
	volatile uint32_t RSVD_3566;	 // 0x3800 Reserved 3566.
	volatile uint32_t RSVD_3567;	 // 0x3804 Reserved 3567.
	volatile uint32_t RSVD_3568;	 // 0x3808 Reserved 3568.
	volatile uint32_t RSVD_3569;	 // 0x380c Reserved 3569.
	volatile uint32_t RSVD_3570;	 // 0x3810 Reserved 3570.
	volatile uint32_t RSVD_3571;	 // 0x3814 Reserved 3571.
	volatile uint32_t RSVD_3572;	 // 0x3818 Reserved 3572.
	volatile uint32_t RSVD_3573;	 // 0x381c Reserved 3573.
	volatile uint32_t RSVD_3574;	 // 0x3820 Reserved 3574.
	volatile uint32_t RSVD_3575;	 // 0x3824 Reserved 3575.
	volatile uint32_t RSVD_3576;	 // 0x3828 Reserved 3576.
	volatile uint32_t RSVD_3577;	 // 0x382c Reserved 3577.
	volatile uint32_t RSVD_3578;	 // 0x3830 Reserved 3578.
	volatile uint32_t RSVD_3579;	 // 0x3834 Reserved 3579.
	volatile uint32_t RSVD_3580;	 // 0x3838 Reserved 3580.
	volatile uint32_t RSVD_3581;	 // 0x383c Reserved 3581.
	volatile uint32_t RSVD_3582;	 // 0x3840 Reserved 3582.
	volatile uint32_t RSVD_3583;	 // 0x3844 Reserved 3583.
	volatile uint32_t RSVD_3584;	 // 0x3848 Reserved 3584.
	volatile uint32_t RSVD_3585;	 // 0x384c Reserved 3585.
	volatile uint32_t RSVD_3586;	 // 0x3850 Reserved 3586.
	volatile uint32_t RSVD_3587;	 // 0x3854 Reserved 3587.
	volatile uint32_t RSVD_3588;	 // 0x3858 Reserved 3588.
	volatile uint32_t RSVD_3589;	 // 0x385c Reserved 3589.
	volatile uint32_t RSVD_3590;	 // 0x3860 Reserved 3590.
	volatile uint32_t RSVD_3591;	 // 0x3864 Reserved 3591.
	volatile uint32_t RSVD_3592;	 // 0x3868 Reserved 3592.
	volatile uint32_t RSVD_3593;	 // 0x386c Reserved 3593.
	volatile uint32_t RSVD_3594;	 // 0x3870 Reserved 3594.
	volatile uint32_t RSVD_3595;	 // 0x3874 Reserved 3595.
	volatile uint32_t RSVD_3596;	 // 0x3878 Reserved 3596.
	volatile uint32_t RSVD_3597;	 // 0x387c Reserved 3597.
	volatile uint32_t RSVD_3598;	 // 0x3880 Reserved 3598.
	volatile uint32_t RSVD_3599;	 // 0x3884 Reserved 3599.
	volatile uint32_t RSVD_3600;	 // 0x3888 Reserved 3600.
	volatile uint32_t RSVD_3601;	 // 0x388c Reserved 3601.
	volatile uint32_t RSVD_3602;	 // 0x3890 Reserved 3602.
	volatile uint32_t RSVD_3603;	 // 0x3894 Reserved 3603.
	volatile uint32_t RSVD_3604;	 // 0x3898 Reserved 3604.
	volatile uint32_t RSVD_3605;	 // 0x389c Reserved 3605.
	volatile uint32_t RSVD_3606;	 // 0x38a0 Reserved 3606.
	volatile uint32_t RSVD_3607;	 // 0x38a4 Reserved 3607.
	volatile uint32_t RSVD_3608;	 // 0x38a8 Reserved 3608.
	volatile uint32_t RSVD_3609;	 // 0x38ac Reserved 3609.
	volatile uint32_t RSVD_3610;	 // 0x38b0 Reserved 3610.
	volatile uint32_t RSVD_3611;	 // 0x38b4 Reserved 3611.
	volatile uint32_t RSVD_3612;	 // 0x38b8 Reserved 3612.
	volatile uint32_t RSVD_3613;	 // 0x38bc Reserved 3613.
	volatile uint32_t RSVD_3614;	 // 0x38c0 Reserved 3614.
	volatile uint32_t RSVD_3615;	 // 0x38c4 Reserved 3615.
	volatile uint32_t RSVD_3616;	 // 0x38c8 Reserved 3616.
	volatile uint32_t RSVD_3617;	 // 0x38cc Reserved 3617.
	volatile uint32_t RSVD_3618;	 // 0x38d0 Reserved 3618.
	volatile uint32_t RSVD_3619;	 // 0x38d4 Reserved 3619.
	volatile uint32_t RSVD_3620;	 // 0x38d8 Reserved 3620.
	volatile uint32_t RSVD_3621;	 // 0x38dc Reserved 3621.
	volatile uint32_t RSVD_3622;	 // 0x38e0 Reserved 3622.
	volatile uint32_t RSVD_3623;	 // 0x38e4 Reserved 3623.
	volatile uint32_t RSVD_3624;	 // 0x38e8 Reserved 3624.
	volatile uint32_t RSVD_3625;	 // 0x38ec Reserved 3625.
	volatile uint32_t RSVD_3626;	 // 0x38f0 Reserved 3626.
	volatile uint32_t RSVD_3627;	 // 0x38f4 Reserved 3627.
	volatile uint32_t RSVD_3628;	 // 0x38f8 Reserved 3628.
	volatile uint32_t RSVD_3629;	 // 0x38fc Reserved 3629.
	volatile uint32_t RSVD_3630;	 // 0x3900 Reserved 3630.
	volatile uint32_t RSVD_3631;	 // 0x3904 Reserved 3631.
	volatile uint32_t RSVD_3632;	 // 0x3908 Reserved 3632.
	volatile uint32_t RSVD_3633;	 // 0x390c Reserved 3633.
	volatile uint32_t RSVD_3634;	 // 0x3910 Reserved 3634.
	volatile uint32_t RSVD_3635;	 // 0x3914 Reserved 3635.
	volatile uint32_t RSVD_3636;	 // 0x3918 Reserved 3636.
	volatile uint32_t RSVD_3637;	 // 0x391c Reserved 3637.
	volatile uint32_t RSVD_3638;	 // 0x3920 Reserved 3638.
	volatile uint32_t RSVD_3639;	 // 0x3924 Reserved 3639.
	volatile uint32_t RSVD_3640;	 // 0x3928 Reserved 3640.
	volatile uint32_t RSVD_3641;	 // 0x392c Reserved 3641.
	volatile uint32_t RSVD_3642;	 // 0x3930 Reserved 3642.
	volatile uint32_t RSVD_3643;	 // 0x3934 Reserved 3643.
	volatile uint32_t RSVD_3644;	 // 0x3938 Reserved 3644.
	volatile uint32_t RSVD_3645;	 // 0x393c Reserved 3645.
	volatile uint32_t RSVD_3646;	 // 0x3940 Reserved 3646.
	volatile uint32_t RSVD_3647;	 // 0x3944 Reserved 3647.
	volatile uint32_t RSVD_3648;	 // 0x3948 Reserved 3648.
	volatile uint32_t RSVD_3649;	 // 0x394c Reserved 3649.
	volatile uint32_t RSVD_3650;	 // 0x3950 Reserved 3650.
	volatile uint32_t RSVD_3651;	 // 0x3954 Reserved 3651.
	volatile uint32_t RSVD_3652;	 // 0x3958 Reserved 3652.
	volatile uint32_t RSVD_3653;	 // 0x395c Reserved 3653.
	volatile uint32_t RSVD_3654;	 // 0x3960 Reserved 3654.
	volatile uint32_t RSVD_3655;	 // 0x3964 Reserved 3655.
	volatile uint32_t RSVD_3656;	 // 0x3968 Reserved 3656.
	volatile uint32_t RSVD_3657;	 // 0x396c Reserved 3657.
	volatile uint32_t RSVD_3658;	 // 0x3970 Reserved 3658.
	volatile uint32_t RSVD_3659;	 // 0x3974 Reserved 3659.
	volatile uint32_t RSVD_3660;	 // 0x3978 Reserved 3660.
	volatile uint32_t RSVD_3661;	 // 0x397c Reserved 3661.
	volatile uint32_t RSVD_3662;	 // 0x3980 Reserved 3662.
	volatile uint32_t RSVD_3663;	 // 0x3984 Reserved 3663.
	volatile uint32_t RSVD_3664;	 // 0x3988 Reserved 3664.
	volatile uint32_t RSVD_3665;	 // 0x398c Reserved 3665.
	volatile uint32_t RSVD_3666;	 // 0x3990 Reserved 3666.
	volatile uint32_t RSVD_3667;	 // 0x3994 Reserved 3667.
	volatile uint32_t RSVD_3668;	 // 0x3998 Reserved 3668.
	volatile uint32_t RSVD_3669;	 // 0x399c Reserved 3669.
	volatile uint32_t RSVD_3670;	 // 0x39a0 Reserved 3670.
	volatile uint32_t RSVD_3671;	 // 0x39a4 Reserved 3671.
	volatile uint32_t RSVD_3672;	 // 0x39a8 Reserved 3672.
	volatile uint32_t RSVD_3673;	 // 0x39ac Reserved 3673.
	volatile uint32_t RSVD_3674;	 // 0x39b0 Reserved 3674.
	volatile uint32_t RSVD_3675;	 // 0x39b4 Reserved 3675.
	volatile uint32_t RSVD_3676;	 // 0x39b8 Reserved 3676.
	volatile uint32_t RSVD_3677;	 // 0x39bc Reserved 3677.
	volatile uint32_t RSVD_3678;	 // 0x39c0 Reserved 3678.
	volatile uint32_t RSVD_3679;	 // 0x39c4 Reserved 3679.
	volatile uint32_t RSVD_3680;	 // 0x39c8 Reserved 3680.
	volatile uint32_t RSVD_3681;	 // 0x39cc Reserved 3681.
	volatile uint32_t RSVD_3682;	 // 0x39d0 Reserved 3682.
	volatile uint32_t RSVD_3683;	 // 0x39d4 Reserved 3683.
	volatile uint32_t RSVD_3684;	 // 0x39d8 Reserved 3684.
	volatile uint32_t RSVD_3685;	 // 0x39dc Reserved 3685.
	volatile uint32_t RSVD_3686;	 // 0x39e0 Reserved 3686.
	volatile uint32_t RSVD_3687;	 // 0x39e4 Reserved 3687.
	volatile uint32_t RSVD_3688;	 // 0x39e8 Reserved 3688.
	volatile uint32_t RSVD_3689;	 // 0x39ec Reserved 3689.
	volatile uint32_t RSVD_3690;	 // 0x39f0 Reserved 3690.
	volatile uint32_t RSVD_3691;	 // 0x39f4 Reserved 3691.
	volatile uint32_t RSVD_3692;	 // 0x39f8 Reserved 3692.
	volatile uint32_t RSVD_3693;	 // 0x39fc Reserved 3693.
	volatile uint32_t RSVD_3694;	 // 0x3a00 Reserved 3694.
	volatile uint32_t RSVD_3695;	 // 0x3a04 Reserved 3695.
	volatile uint32_t RSVD_3696;	 // 0x3a08 Reserved 3696.
	volatile uint32_t RSVD_3697;	 // 0x3a0c Reserved 3697.
	volatile uint32_t RSVD_3698;	 // 0x3a10 Reserved 3698.
	volatile uint32_t RSVD_3699;	 // 0x3a14 Reserved 3699.
	volatile uint32_t RSVD_3700;	 // 0x3a18 Reserved 3700.
	volatile uint32_t RSVD_3701;	 // 0x3a1c Reserved 3701.
	volatile uint32_t RSVD_3702;	 // 0x3a20 Reserved 3702.
	volatile uint32_t RSVD_3703;	 // 0x3a24 Reserved 3703.
	volatile uint32_t RSVD_3704;	 // 0x3a28 Reserved 3704.
	volatile uint32_t RSVD_3705;	 // 0x3a2c Reserved 3705.
	volatile uint32_t RSVD_3706;	 // 0x3a30 Reserved 3706.
	volatile uint32_t RSVD_3707;	 // 0x3a34 Reserved 3707.
	volatile uint32_t RSVD_3708;	 // 0x3a38 Reserved 3708.
	volatile uint32_t RSVD_3709;	 // 0x3a3c Reserved 3709.
	volatile uint32_t RSVD_3710;	 // 0x3a40 Reserved 3710.
	volatile uint32_t RSVD_3711;	 // 0x3a44 Reserved 3711.
	volatile uint32_t RSVD_3712;	 // 0x3a48 Reserved 3712.
	volatile uint32_t RSVD_3713;	 // 0x3a4c Reserved 3713.
	volatile uint32_t RSVD_3714;	 // 0x3a50 Reserved 3714.
	volatile uint32_t RSVD_3715;	 // 0x3a54 Reserved 3715.
	volatile uint32_t RSVD_3716;	 // 0x3a58 Reserved 3716.
	volatile uint32_t RSVD_3717;	 // 0x3a5c Reserved 3717.
	volatile uint32_t RSVD_3718;	 // 0x3a60 Reserved 3718.
	volatile uint32_t RSVD_3719;	 // 0x3a64 Reserved 3719.
	volatile uint32_t RSVD_3720;	 // 0x3a68 Reserved 3720.
	volatile uint32_t RSVD_3721;	 // 0x3a6c Reserved 3721.
	volatile uint32_t RSVD_3722;	 // 0x3a70 Reserved 3722.
	volatile uint32_t RSVD_3723;	 // 0x3a74 Reserved 3723.
	volatile uint32_t RSVD_3724;	 // 0x3a78 Reserved 3724.
	volatile uint32_t RSVD_3725;	 // 0x3a7c Reserved 3725.
	volatile uint32_t RSVD_3726;	 // 0x3a80 Reserved 3726.
	volatile uint32_t RSVD_3727;	 // 0x3a84 Reserved 3727.
	volatile uint32_t RSVD_3728;	 // 0x3a88 Reserved 3728.
	volatile uint32_t RSVD_3729;	 // 0x3a8c Reserved 3729.
	volatile uint32_t RSVD_3730;	 // 0x3a90 Reserved 3730.
	volatile uint32_t RSVD_3731;	 // 0x3a94 Reserved 3731.
	volatile uint32_t RSVD_3732;	 // 0x3a98 Reserved 3732.
	volatile uint32_t RSVD_3733;	 // 0x3a9c Reserved 3733.
	volatile uint32_t RSVD_3734;	 // 0x3aa0 Reserved 3734.
	volatile uint32_t RSVD_3735;	 // 0x3aa4 Reserved 3735.
	volatile uint32_t RSVD_3736;	 // 0x3aa8 Reserved 3736.
	volatile uint32_t RSVD_3737;	 // 0x3aac Reserved 3737.
	volatile uint32_t RSVD_3738;	 // 0x3ab0 Reserved 3738.
	volatile uint32_t RSVD_3739;	 // 0x3ab4 Reserved 3739.
	volatile uint32_t RSVD_3740;	 // 0x3ab8 Reserved 3740.
	volatile uint32_t RSVD_3741;	 // 0x3abc Reserved 3741.
	volatile uint32_t RSVD_3742;	 // 0x3ac0 Reserved 3742.
	volatile uint32_t RSVD_3743;	 // 0x3ac4 Reserved 3743.
	volatile uint32_t RSVD_3744;	 // 0x3ac8 Reserved 3744.
	volatile uint32_t RSVD_3745;	 // 0x3acc Reserved 3745.
	volatile uint32_t RSVD_3746;	 // 0x3ad0 Reserved 3746.
	volatile uint32_t RSVD_3747;	 // 0x3ad4 Reserved 3747.
	volatile uint32_t RSVD_3748;	 // 0x3ad8 Reserved 3748.
	volatile uint32_t RSVD_3749;	 // 0x3adc Reserved 3749.
	volatile uint32_t RSVD_3750;	 // 0x3ae0 Reserved 3750.
	volatile uint32_t RSVD_3751;	 // 0x3ae4 Reserved 3751.
	volatile uint32_t RSVD_3752;	 // 0x3ae8 Reserved 3752.
	volatile uint32_t RSVD_3753;	 // 0x3aec Reserved 3753.
	volatile uint32_t RSVD_3754;	 // 0x3af0 Reserved 3754.
	volatile uint32_t RSVD_3755;	 // 0x3af4 Reserved 3755.
	volatile uint32_t RSVD_3756;	 // 0x3af8 Reserved 3756.
	volatile uint32_t RSVD_3757;	 // 0x3afc Reserved 3757.
	volatile uint32_t RSVD_3758;	 // 0x3b00 Reserved 3758.
	volatile uint32_t RSVD_3759;	 // 0x3b04 Reserved 3759.
	volatile uint32_t RSVD_3760;	 // 0x3b08 Reserved 3760.
	volatile uint32_t RSVD_3761;	 // 0x3b0c Reserved 3761.
	volatile uint32_t RSVD_3762;	 // 0x3b10 Reserved 3762.
	volatile uint32_t RSVD_3763;	 // 0x3b14 Reserved 3763.
	volatile uint32_t RSVD_3764;	 // 0x3b18 Reserved 3764.
	volatile uint32_t RSVD_3765;	 // 0x3b1c Reserved 3765.
	volatile uint32_t RSVD_3766;	 // 0x3b20 Reserved 3766.
	volatile uint32_t RSVD_3767;	 // 0x3b24 Reserved 3767.
	volatile uint32_t RSVD_3768;	 // 0x3b28 Reserved 3768.
	volatile uint32_t RSVD_3769;	 // 0x3b2c Reserved 3769.
	volatile uint32_t RSVD_3770;	 // 0x3b30 Reserved 3770.
	volatile uint32_t RSVD_3771;	 // 0x3b34 Reserved 3771.
	volatile uint32_t RSVD_3772;	 // 0x3b38 Reserved 3772.
	volatile uint32_t RSVD_3773;	 // 0x3b3c Reserved 3773.
	volatile uint32_t RSVD_3774;	 // 0x3b40 Reserved 3774.
	volatile uint32_t RSVD_3775;	 // 0x3b44 Reserved 3775.
	volatile uint32_t RSVD_3776;	 // 0x3b48 Reserved 3776.
	volatile uint32_t RSVD_3777;	 // 0x3b4c Reserved 3777.
	volatile uint32_t RSVD_3778;	 // 0x3b50 Reserved 3778.
	volatile uint32_t RSVD_3779;	 // 0x3b54 Reserved 3779.
	volatile uint32_t RSVD_3780;	 // 0x3b58 Reserved 3780.
	volatile uint32_t RSVD_3781;	 // 0x3b5c Reserved 3781.
	volatile uint32_t RSVD_3782;	 // 0x3b60 Reserved 3782.
	volatile uint32_t RSVD_3783;	 // 0x3b64 Reserved 3783.
	volatile uint32_t RSVD_3784;	 // 0x3b68 Reserved 3784.
	volatile uint32_t RSVD_3785;	 // 0x3b6c Reserved 3785.
	volatile uint32_t RSVD_3786;	 // 0x3b70 Reserved 3786.
	volatile uint32_t RSVD_3787;	 // 0x3b74 Reserved 3787.
	volatile uint32_t RSVD_3788;	 // 0x3b78 Reserved 3788.
	volatile uint32_t RSVD_3789;	 // 0x3b7c Reserved 3789.
	volatile uint32_t RSVD_3790;	 // 0x3b80 Reserved 3790.
	volatile uint32_t RSVD_3791;	 // 0x3b84 Reserved 3791.
	volatile uint32_t RSVD_3792;	 // 0x3b88 Reserved 3792.
	volatile uint32_t RSVD_3793;	 // 0x3b8c Reserved 3793.
	volatile uint32_t RSVD_3794;	 // 0x3b90 Reserved 3794.
	volatile uint32_t RSVD_3795;	 // 0x3b94 Reserved 3795.
	volatile uint32_t RSVD_3796;	 // 0x3b98 Reserved 3796.
	volatile uint32_t RSVD_3797;	 // 0x3b9c Reserved 3797.
	volatile uint32_t RSVD_3798;	 // 0x3ba0 Reserved 3798.
	volatile uint32_t RSVD_3799;	 // 0x3ba4 Reserved 3799.
	volatile uint32_t RSVD_3800;	 // 0x3ba8 Reserved 3800.
	volatile uint32_t RSVD_3801;	 // 0x3bac Reserved 3801.
	volatile uint32_t RSVD_3802;	 // 0x3bb0 Reserved 3802.
	volatile uint32_t RSVD_3803;	 // 0x3bb4 Reserved 3803.
	volatile uint32_t RSVD_3804;	 // 0x3bb8 Reserved 3804.
	volatile uint32_t RSVD_3805;	 // 0x3bbc Reserved 3805.
	volatile uint32_t RSVD_3806;	 // 0x3bc0 Reserved 3806.
	volatile uint32_t RSVD_3807;	 // 0x3bc4 Reserved 3807.
	volatile uint32_t RSVD_3808;	 // 0x3bc8 Reserved 3808.
	volatile uint32_t RSVD_3809;	 // 0x3bcc Reserved 3809.
	volatile uint32_t RSVD_3810;	 // 0x3bd0 Reserved 3810.
	volatile uint32_t RSVD_3811;	 // 0x3bd4 Reserved 3811.
	volatile uint32_t RSVD_3812;	 // 0x3bd8 Reserved 3812.
	volatile uint32_t RSVD_3813;	 // 0x3bdc Reserved 3813.
	volatile uint32_t RSVD_3814;	 // 0x3be0 Reserved 3814.
	volatile uint32_t RSVD_3815;	 // 0x3be4 Reserved 3815.
	volatile uint32_t RSVD_3816;	 // 0x3be8 Reserved 3816.
	volatile uint32_t RSVD_3817;	 // 0x3bec Reserved 3817.
	volatile uint32_t RSVD_3818;	 // 0x3bf0 Reserved 3818.
	volatile uint32_t RSVD_3819;	 // 0x3bf4 Reserved 3819.
	volatile uint32_t RSVD_3820;	 // 0x3bf8 Reserved 3820.
	volatile uint32_t RSVD_3821;	 // 0x3bfc Reserved 3821.
	volatile uint32_t RSVD_3822;	 // 0x3c00 Reserved 3822.
	volatile uint32_t RSVD_3823;	 // 0x3c04 Reserved 3823.
	volatile uint32_t RSVD_3824;	 // 0x3c08 Reserved 3824.
	volatile uint32_t RSVD_3825;	 // 0x3c0c Reserved 3825.
	volatile uint32_t RSVD_3826;	 // 0x3c10 Reserved 3826.
	volatile uint32_t RSVD_3827;	 // 0x3c14 Reserved 3827.
	volatile uint32_t RSVD_3828;	 // 0x3c18 Reserved 3828.
	volatile uint32_t RSVD_3829;	 // 0x3c1c Reserved 3829.
	volatile uint32_t RSVD_3830;	 // 0x3c20 Reserved 3830.
	volatile uint32_t RSVD_3831;	 // 0x3c24 Reserved 3831.
	volatile uint32_t RSVD_3832;	 // 0x3c28 Reserved 3832.
	volatile uint32_t RSVD_3833;	 // 0x3c2c Reserved 3833.
	volatile uint32_t RSVD_3834;	 // 0x3c30 Reserved 3834.
	volatile uint32_t RSVD_3835;	 // 0x3c34 Reserved 3835.
	volatile uint32_t RSVD_3836;	 // 0x3c38 Reserved 3836.
	volatile uint32_t RSVD_3837;	 // 0x3c3c Reserved 3837.
	volatile uint32_t RSVD_3838;	 // 0x3c40 Reserved 3838.
	volatile uint32_t RSVD_3839;	 // 0x3c44 Reserved 3839.
	volatile uint32_t RSVD_3840;	 // 0x3c48 Reserved 3840.
	volatile uint32_t RSVD_3841;	 // 0x3c4c Reserved 3841.
	volatile uint32_t RSVD_3842;	 // 0x3c50 Reserved 3842.
	volatile uint32_t RSVD_3843;	 // 0x3c54 Reserved 3843.
	volatile uint32_t RSVD_3844;	 // 0x3c58 Reserved 3844.
	volatile uint32_t RSVD_3845;	 // 0x3c5c Reserved 3845.
	volatile uint32_t RSVD_3846;	 // 0x3c60 Reserved 3846.
	volatile uint32_t RSVD_3847;	 // 0x3c64 Reserved 3847.
	volatile uint32_t RSVD_3848;	 // 0x3c68 Reserved 3848.
	volatile uint32_t RSVD_3849;	 // 0x3c6c Reserved 3849.
	volatile uint32_t RSVD_3850;	 // 0x3c70 Reserved 3850.
	volatile uint32_t RSVD_3851;	 // 0x3c74 Reserved 3851.
	volatile uint32_t RSVD_3852;	 // 0x3c78 Reserved 3852.
	volatile uint32_t RSVD_3853;	 // 0x3c7c Reserved 3853.
	volatile uint32_t RSVD_3854;	 // 0x3c80 Reserved 3854.
	volatile uint32_t RSVD_3855;	 // 0x3c84 Reserved 3855.
	volatile uint32_t RSVD_3856;	 // 0x3c88 Reserved 3856.
	volatile uint32_t RSVD_3857;	 // 0x3c8c Reserved 3857.
	volatile uint32_t RSVD_3858;	 // 0x3c90 Reserved 3858.
	volatile uint32_t RSVD_3859;	 // 0x3c94 Reserved 3859.
	volatile uint32_t RSVD_3860;	 // 0x3c98 Reserved 3860.
	volatile uint32_t RSVD_3861;	 // 0x3c9c Reserved 3861.
	volatile uint32_t RSVD_3862;	 // 0x3ca0 Reserved 3862.
	volatile uint32_t RSVD_3863;	 // 0x3ca4 Reserved 3863.
	volatile uint32_t RSVD_3864;	 // 0x3ca8 Reserved 3864.
	volatile uint32_t RSVD_3865;	 // 0x3cac Reserved 3865.
	volatile uint32_t RSVD_3866;	 // 0x3cb0 Reserved 3866.
	volatile uint32_t RSVD_3867;	 // 0x3cb4 Reserved 3867.
	volatile uint32_t RSVD_3868;	 // 0x3cb8 Reserved 3868.
	volatile uint32_t RSVD_3869;	 // 0x3cbc Reserved 3869.
	volatile uint32_t RSVD_3870;	 // 0x3cc0 Reserved 3870.
	volatile uint32_t RSVD_3871;	 // 0x3cc4 Reserved 3871.
	volatile uint32_t RSVD_3872;	 // 0x3cc8 Reserved 3872.
	volatile uint32_t RSVD_3873;	 // 0x3ccc Reserved 3873.
	volatile uint32_t RSVD_3874;	 // 0x3cd0 Reserved 3874.
	volatile uint32_t RSVD_3875;	 // 0x3cd4 Reserved 3875.
	volatile uint32_t RSVD_3876;	 // 0x3cd8 Reserved 3876.
	volatile uint32_t RSVD_3877;	 // 0x3cdc Reserved 3877.
	volatile uint32_t RSVD_3878;	 // 0x3ce0 Reserved 3878.
	volatile uint32_t RSVD_3879;	 // 0x3ce4 Reserved 3879.
	volatile uint32_t RSVD_3880;	 // 0x3ce8 Reserved 3880.
	volatile uint32_t RSVD_3881;	 // 0x3cec Reserved 3881.
	volatile uint32_t RSVD_3882;	 // 0x3cf0 Reserved 3882.
	volatile uint32_t RSVD_3883;	 // 0x3cf4 Reserved 3883.
	volatile uint32_t RSVD_3884;	 // 0x3cf8 Reserved 3884.
	volatile uint32_t RSVD_3885;	 // 0x3cfc Reserved 3885.
	volatile uint32_t RSVD_3886;	 // 0x3d00 Reserved 3886.
	volatile uint32_t RSVD_3887;	 // 0x3d04 Reserved 3887.
	volatile uint32_t RSVD_3888;	 // 0x3d08 Reserved 3888.
	volatile uint32_t RSVD_3889;	 // 0x3d0c Reserved 3889.
	volatile uint32_t RSVD_3890;	 // 0x3d10 Reserved 3890.
	volatile uint32_t RSVD_3891;	 // 0x3d14 Reserved 3891.
	volatile uint32_t RSVD_3892;	 // 0x3d18 Reserved 3892.
	volatile uint32_t RSVD_3893;	 // 0x3d1c Reserved 3893.
	volatile uint32_t RSVD_3894;	 // 0x3d20 Reserved 3894.
	volatile uint32_t RSVD_3895;	 // 0x3d24 Reserved 3895.
	volatile uint32_t RSVD_3896;	 // 0x3d28 Reserved 3896.
	volatile uint32_t RSVD_3897;	 // 0x3d2c Reserved 3897.
	volatile uint32_t RSVD_3898;	 // 0x3d30 Reserved 3898.
	volatile uint32_t RSVD_3899;	 // 0x3d34 Reserved 3899.
	volatile uint32_t RSVD_3900;	 // 0x3d38 Reserved 3900.
	volatile uint32_t RSVD_3901;	 // 0x3d3c Reserved 3901.
	volatile uint32_t RSVD_3902;	 // 0x3d40 Reserved 3902.
	volatile uint32_t RSVD_3903;	 // 0x3d44 Reserved 3903.
	volatile uint32_t RSVD_3904;	 // 0x3d48 Reserved 3904.
	volatile uint32_t RSVD_3905;	 // 0x3d4c Reserved 3905.
	volatile uint32_t RSVD_3906;	 // 0x3d50 Reserved 3906.
	volatile uint32_t RSVD_3907;	 // 0x3d54 Reserved 3907.
	volatile uint32_t RSVD_3908;	 // 0x3d58 Reserved 3908.
	volatile uint32_t RSVD_3909;	 // 0x3d5c Reserved 3909.
	volatile uint32_t RSVD_3910;	 // 0x3d60 Reserved 3910.
	volatile uint32_t RSVD_3911;	 // 0x3d64 Reserved 3911.
	volatile uint32_t RSVD_3912;	 // 0x3d68 Reserved 3912.
	volatile uint32_t RSVD_3913;	 // 0x3d6c Reserved 3913.
	volatile uint32_t RSVD_3914;	 // 0x3d70 Reserved 3914.
	volatile uint32_t RSVD_3915;	 // 0x3d74 Reserved 3915.
	volatile uint32_t RSVD_3916;	 // 0x3d78 Reserved 3916.
	volatile uint32_t RSVD_3917;	 // 0x3d7c Reserved 3917.
	volatile uint32_t RSVD_3918;	 // 0x3d80 Reserved 3918.
	volatile uint32_t RSVD_3919;	 // 0x3d84 Reserved 3919.
	volatile uint32_t RSVD_3920;	 // 0x3d88 Reserved 3920.
	volatile uint32_t RSVD_3921;	 // 0x3d8c Reserved 3921.
	volatile uint32_t RSVD_3922;	 // 0x3d90 Reserved 3922.
	volatile uint32_t RSVD_3923;	 // 0x3d94 Reserved 3923.
	volatile uint32_t RSVD_3924;	 // 0x3d98 Reserved 3924.
	volatile uint32_t RSVD_3925;	 // 0x3d9c Reserved 3925.
	volatile uint32_t RSVD_3926;	 // 0x3da0 Reserved 3926.
	volatile uint32_t RSVD_3927;	 // 0x3da4 Reserved 3927.
	volatile uint32_t RSVD_3928;	 // 0x3da8 Reserved 3928.
	volatile uint32_t RSVD_3929;	 // 0x3dac Reserved 3929.
	volatile uint32_t RSVD_3930;	 // 0x3db0 Reserved 3930.
	volatile uint32_t RSVD_3931;	 // 0x3db4 Reserved 3931.
	volatile uint32_t RSVD_3932;	 // 0x3db8 Reserved 3932.
	volatile uint32_t RSVD_3933;	 // 0x3dbc Reserved 3933.
	volatile uint32_t RSVD_3934;	 // 0x3dc0 Reserved 3934.
	volatile uint32_t RSVD_3935;	 // 0x3dc4 Reserved 3935.
	volatile uint32_t RSVD_3936;	 // 0x3dc8 Reserved 3936.
	volatile uint32_t RSVD_3937;	 // 0x3dcc Reserved 3937.
	volatile uint32_t RSVD_3938;	 // 0x3dd0 Reserved 3938.
	volatile uint32_t RSVD_3939;	 // 0x3dd4 Reserved 3939.
	volatile uint32_t RSVD_3940;	 // 0x3dd8 Reserved 3940.
	volatile uint32_t RSVD_3941;	 // 0x3ddc Reserved 3941.
	volatile uint32_t RSVD_3942;	 // 0x3de0 Reserved 3942.
	volatile uint32_t RSVD_3943;	 // 0x3de4 Reserved 3943.
	volatile uint32_t RSVD_3944;	 // 0x3de8 Reserved 3944.
	volatile uint32_t RSVD_3945;	 // 0x3dec Reserved 3945.
	volatile uint32_t RSVD_3946;	 // 0x3df0 Reserved 3946.
	volatile uint32_t RSVD_3947;	 // 0x3df4 Reserved 3947.
	volatile uint32_t RSVD_3948;	 // 0x3df8 Reserved 3948.
	volatile uint32_t RSVD_3949;	 // 0x3dfc Reserved 3949.
	volatile uint32_t RSVD_3950;	 // 0x3e00 Reserved 3950.
	volatile uint32_t RSVD_3951;	 // 0x3e04 Reserved 3951.
	volatile uint32_t RSVD_3952;	 // 0x3e08 Reserved 3952.
	volatile uint32_t RSVD_3953;	 // 0x3e0c Reserved 3953.
	volatile uint32_t RSVD_3954;	 // 0x3e10 Reserved 3954.
	volatile uint32_t RSVD_3955;	 // 0x3e14 Reserved 3955.
	volatile uint32_t RSVD_3956;	 // 0x3e18 Reserved 3956.
	volatile uint32_t RSVD_3957;	 // 0x3e1c Reserved 3957.
	volatile uint32_t RSVD_3958;	 // 0x3e20 Reserved 3958.
	volatile uint32_t RSVD_3959;	 // 0x3e24 Reserved 3959.
	volatile uint32_t RSVD_3960;	 // 0x3e28 Reserved 3960.
	volatile uint32_t RSVD_3961;	 // 0x3e2c Reserved 3961.
	volatile uint32_t RSVD_3962;	 // 0x3e30 Reserved 3962.
	volatile uint32_t RSVD_3963;	 // 0x3e34 Reserved 3963.
	volatile uint32_t RSVD_3964;	 // 0x3e38 Reserved 3964.
	volatile uint32_t RSVD_3965;	 // 0x3e3c Reserved 3965.
	volatile uint32_t RSVD_3966;	 // 0x3e40 Reserved 3966.
	volatile uint32_t RSVD_3967;	 // 0x3e44 Reserved 3967.
	volatile uint32_t RSVD_3968;	 // 0x3e48 Reserved 3968.
	volatile uint32_t RSVD_3969;	 // 0x3e4c Reserved 3969.
	volatile uint32_t RSVD_3970;	 // 0x3e50 Reserved 3970.
	volatile uint32_t RSVD_3971;	 // 0x3e54 Reserved 3971.
	volatile uint32_t RSVD_3972;	 // 0x3e58 Reserved 3972.
	volatile uint32_t RSVD_3973;	 // 0x3e5c Reserved 3973.
	volatile uint32_t RSVD_3974;	 // 0x3e60 Reserved 3974.
	volatile uint32_t RSVD_3975;	 // 0x3e64 Reserved 3975.
	volatile uint32_t RSVD_3976;	 // 0x3e68 Reserved 3976.
	volatile uint32_t RSVD_3977;	 // 0x3e6c Reserved 3977.
	volatile uint32_t RSVD_3978;	 // 0x3e70 Reserved 3978.
	volatile uint32_t RSVD_3979;	 // 0x3e74 Reserved 3979.
	volatile uint32_t RSVD_3980;	 // 0x3e78 Reserved 3980.
	volatile uint32_t RSVD_3981;	 // 0x3e7c Reserved 3981.
	volatile uint32_t RSVD_3982;	 // 0x3e80 Reserved 3982.
	volatile uint32_t RSVD_3983;	 // 0x3e84 Reserved 3983.
	volatile uint32_t RSVD_3984;	 // 0x3e88 Reserved 3984.
	volatile uint32_t RSVD_3985;	 // 0x3e8c Reserved 3985.
	volatile uint32_t RSVD_3986;	 // 0x3e90 Reserved 3986.
	volatile uint32_t RSVD_3987;	 // 0x3e94 Reserved 3987.
	volatile uint32_t RSVD_3988;	 // 0x3e98 Reserved 3988.
	volatile uint32_t RSVD_3989;	 // 0x3e9c Reserved 3989.
	volatile uint32_t RSVD_3990;	 // 0x3ea0 Reserved 3990.
	volatile uint32_t RSVD_3991;	 // 0x3ea4 Reserved 3991.
	volatile uint32_t RSVD_3992;	 // 0x3ea8 Reserved 3992.
	volatile uint32_t RSVD_3993;	 // 0x3eac Reserved 3993.
	volatile uint32_t RSVD_3994;	 // 0x3eb0 Reserved 3994.
	volatile uint32_t RSVD_3995;	 // 0x3eb4 Reserved 3995.
	volatile uint32_t RSVD_3996;	 // 0x3eb8 Reserved 3996.
	volatile uint32_t RSVD_3997;	 // 0x3ebc Reserved 3997.
	volatile uint32_t RSVD_3998;	 // 0x3ec0 Reserved 3998.
	volatile uint32_t RSVD_3999;	 // 0x3ec4 Reserved 3999.
	volatile uint32_t RSVD_4000;	 // 0x3ec8 Reserved 4000.
	volatile uint32_t RSVD_4001;	 // 0x3ecc Reserved 4001.
	volatile uint32_t RSVD_4002;	 // 0x3ed0 Reserved 4002.
	volatile uint32_t RSVD_4003;	 // 0x3ed4 Reserved 4003.
	volatile uint32_t RSVD_4004;	 // 0x3ed8 Reserved 4004.
	volatile uint32_t RSVD_4005;	 // 0x3edc Reserved 4005.
	volatile uint32_t RSVD_4006;	 // 0x3ee0 Reserved 4006.
	volatile uint32_t RSVD_4007;	 // 0x3ee4 Reserved 4007.
	volatile uint32_t RSVD_4008;	 // 0x3ee8 Reserved 4008.
	volatile uint32_t RSVD_4009;	 // 0x3eec Reserved 4009.
	volatile uint32_t RSVD_4010;	 // 0x3ef0 Reserved 4010.
	volatile uint32_t RSVD_4011;	 // 0x3ef4 Reserved 4011.
	volatile uint32_t RSVD_4012;	 // 0x3ef8 Reserved 4012.
	volatile uint32_t RSVD_4013;	 // 0x3efc Reserved 4013.
	volatile uint32_t RSVD_4014;	 // 0x3f00 Reserved 4014.
	volatile uint32_t RSVD_4015;	 // 0x3f04 Reserved 4015.
	volatile uint32_t RSVD_4016;	 // 0x3f08 Reserved 4016.
	volatile uint32_t RSVD_4017;	 // 0x3f0c Reserved 4017.
	volatile uint32_t RSVD_4018;	 // 0x3f10 Reserved 4018.
	volatile uint32_t RSVD_4019;	 // 0x3f14 Reserved 4019.
	volatile uint32_t RSVD_4020;	 // 0x3f18 Reserved 4020.
	volatile uint32_t RSVD_4021;	 // 0x3f1c Reserved 4021.
	volatile uint32_t RSVD_4022;	 // 0x3f20 Reserved 4022.
	volatile uint32_t RSVD_4023;	 // 0x3f24 Reserved 4023.
	volatile uint32_t RSVD_4024;	 // 0x3f28 Reserved 4024.
	volatile uint32_t RSVD_4025;	 // 0x3f2c Reserved 4025.
	volatile uint32_t RSVD_4026;	 // 0x3f30 Reserved 4026.
	volatile uint32_t RSVD_4027;	 // 0x3f34 Reserved 4027.
	volatile uint32_t RSVD_4028;	 // 0x3f38 Reserved 4028.
	volatile uint32_t RSVD_4029;	 // 0x3f3c Reserved 4029.
	volatile uint32_t RSVD_4030;	 // 0x3f40 Reserved 4030.
	volatile uint32_t RSVD_4031;	 // 0x3f44 Reserved 4031.
	volatile uint32_t RSVD_4032;	 // 0x3f48 Reserved 4032.
	volatile uint32_t RSVD_4033;	 // 0x3f4c Reserved 4033.
	volatile uint32_t RSVD_4034;	 // 0x3f50 Reserved 4034.
	volatile uint32_t RSVD_4035;	 // 0x3f54 Reserved 4035.
	volatile uint32_t RSVD_4036;	 // 0x3f58 Reserved 4036.
	volatile uint32_t RSVD_4037;	 // 0x3f5c Reserved 4037.
	volatile uint32_t RSVD_4038;	 // 0x3f60 Reserved 4038.
	volatile uint32_t RSVD_4039;	 // 0x3f64 Reserved 4039.
	volatile uint32_t RSVD_4040;	 // 0x3f68 Reserved 4040.
	volatile uint32_t RSVD_4041;	 // 0x3f6c Reserved 4041.
	volatile uint32_t RSVD_4042;	 // 0x3f70 Reserved 4042.
	volatile uint32_t RSVD_4043;	 // 0x3f74 Reserved 4043.
	volatile uint32_t RSVD_4044;	 // 0x3f78 Reserved 4044.
	volatile uint32_t RSVD_4045;	 // 0x3f7c Reserved 4045.
	volatile uint32_t RSVD_4046;	 // 0x3f80 Reserved 4046.
	volatile uint32_t RSVD_4047;	 // 0x3f84 Reserved 4047.
	volatile uint32_t RSVD_4048;	 // 0x3f88 Reserved 4048.
	volatile uint32_t RSVD_4049;	 // 0x3f8c Reserved 4049.
	volatile uint32_t RSVD_4050;	 // 0x3f90 Reserved 4050.
	volatile uint32_t RSVD_4051;	 // 0x3f94 Reserved 4051.
	volatile uint32_t RSVD_4052;	 // 0x3f98 Reserved 4052.
	volatile uint32_t RSVD_4053;	 // 0x3f9c Reserved 4053.
	volatile uint32_t RSVD_4054;	 // 0x3fa0 Reserved 4054.
	volatile uint32_t RSVD_4055;	 // 0x3fa4 Reserved 4055.
	volatile uint32_t RSVD_4056;	 // 0x3fa8 Reserved 4056.
	volatile uint32_t RSVD_4057;	 // 0x3fac Reserved 4057.
	volatile uint32_t RSVD_4058;	 // 0x3fb0 Reserved 4058.
	volatile uint32_t RSVD_4059;	 // 0x3fb4 Reserved 4059.
	volatile uint32_t RSVD_4060;	 // 0x3fb8 Reserved 4060.
	volatile uint32_t RSVD_4061;	 // 0x3fbc Reserved 4061.
	volatile uint32_t RSVD_4062;	 // 0x3fc0 Reserved 4062.
	volatile uint32_t RSVD_4063;	 // 0x3fc4 Reserved 4063.
	volatile uint32_t RSVD_4064;	 // 0x3fc8 Reserved 4064.
	volatile uint32_t RSVD_4065;	 // 0x3fcc Reserved 4065.
	volatile uint32_t RSVD_4066;	 // 0x3fd0 Reserved 4066.
	volatile uint32_t RSVD_4067;	 // 0x3fd4 Reserved 4067.
	volatile uint32_t RSVD_4068;	 // 0x3fd8 Reserved 4068.
	volatile uint32_t RSVD_4069;	 // 0x3fdc Reserved 4069.
	volatile uint32_t RSVD_4070;	 // 0x3fe0 Reserved 4070.
	volatile uint32_t RSVD_4071;	 // 0x3fe4 Reserved 4071.
	volatile uint32_t RSVD_4072;	 // 0x3fe8 Reserved 4072.
	volatile uint32_t RSVD_4073;	 // 0x3fec Reserved 4073.
	volatile uint32_t RSVD_4074;	 // 0x3ff0 Reserved 4074.
	volatile uint32_t RSVD_4075;	 // 0x3ff4 Reserved 4075.
	volatile uint32_t RSVD_4076;	 // 0x3ff8 Reserved 4076.
	volatile uint32_t RSVD_4077;	 // 0x3ffc Reserved 4077.
	volatile uint32_t DDRPHY_PLL_CTL;	        // 0x4000
	volatile uint32_t DDRPHY_PLL_CTL2;	        // 0x4004
	volatile uint32_t DDRPHY_PLL_CTL3;	        // 0x4008
	volatile uint32_t DDRPHY_PLL_CTL4;	        // 0x400c
	volatile uint32_t DDRPHY_PLL_STATUS;	    // 0x4010
} LPDDR5_SGR_t;

/****************************** Bit definition for PA_QOS_URGENT_CTL register ********************************/

#define PA_QOS_URGENT_CTL_ARPOISON_ENABLE_Pos		(19U)
#define PA_QOS_URGENT_CTL_ARPOISON_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARPOISON_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_ARPOISON_ENABLE    		PA_QOS_URGENT_CTL_ARPOISON_ENABLE_Msk


#define PA_QOS_URGENT_CTL_ARPOISON_Pos		(18U)
#define PA_QOS_URGENT_CTL_ARPOISON_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARPOISON_Pos)
#define PA_QOS_URGENT_CTL_ARPOISON    		PA_QOS_URGENT_CTL_ARPOISON_Msk


#define PA_QOS_URGENT_CTL_AWPOISON_ENABLE_Pos		(17U)
#define PA_QOS_URGENT_CTL_AWPOISON_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_AWPOISON_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_AWPOISON_ENABLE    		PA_QOS_URGENT_CTL_AWPOISON_ENABLE_Msk


#define PA_QOS_URGENT_CTL_AWPOISON_Pos		(16U)
#define PA_QOS_URGENT_CTL_AWPOISON_Msk		(0x1UL << PA_QOS_URGENT_CTL_AWPOISON_Pos)
#define PA_QOS_URGENT_CTL_AWPOISON    		PA_QOS_URGENT_CTL_AWPOISON_Msk


#define PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE_Pos		(15U)
#define PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE    		PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE_Msk


#define PA_QOS_URGENT_CTL_ARRUGENTR_Pos		(14U)
#define PA_QOS_URGENT_CTL_ARRUGENTR_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARRUGENTR_Pos)
#define PA_QOS_URGENT_CTL_ARRUGENTR    		PA_QOS_URGENT_CTL_ARRUGENTR_Msk


#define PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE_Pos		(13U)
#define PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE    		PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE_Msk


#define PA_QOS_URGENT_CTL_ARRUGENTB_Pos		(12U)
#define PA_QOS_URGENT_CTL_ARRUGENTB_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARRUGENTB_Pos)
#define PA_QOS_URGENT_CTL_ARRUGENTB    		PA_QOS_URGENT_CTL_ARRUGENTB_Msk


#define PA_QOS_URGENT_CTL_AWRUGENT_ENABLE_Pos		(11U)
#define PA_QOS_URGENT_CTL_AWRUGENT_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_AWRUGENT_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_AWRUGENT_ENABLE    		PA_QOS_URGENT_CTL_AWRUGENT_ENABLE_Msk


#define PA_QOS_URGENT_CTL_AWURGENT_Pos		(10U)
#define PA_QOS_URGENT_CTL_AWURGENT_Msk		(0x1UL << PA_QOS_URGENT_CTL_AWURGENT_Pos)
#define PA_QOS_URGENT_CTL_AWURGENT    		PA_QOS_URGENT_CTL_AWURGENT_Msk


#define PA_QOS_URGENT_CTL_ARQOS_ENABLE_Pos		(9U)
#define PA_QOS_URGENT_CTL_ARQOS_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_ARQOS_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_ARQOS_ENABLE    		PA_QOS_URGENT_CTL_ARQOS_ENABLE_Msk


#define PA_QOS_URGENT_CTL_ARQOS_Pos		(5U)
#define PA_QOS_URGENT_CTL_ARQOS_Msk		(0xfUL << PA_QOS_URGENT_CTL_ARQOS_Pos)
#define PA_QOS_URGENT_CTL_ARQOS    		PA_QOS_URGENT_CTL_ARQOS_Msk


#define PA_QOS_URGENT_CTL_AWQOS_ENABLE_Pos		(4U)
#define PA_QOS_URGENT_CTL_AWQOS_ENABLE_Msk		(0x1UL << PA_QOS_URGENT_CTL_AWQOS_ENABLE_Pos)
#define PA_QOS_URGENT_CTL_AWQOS_ENABLE    		PA_QOS_URGENT_CTL_AWQOS_ENABLE_Msk


#define PA_QOS_URGENT_CTL_AWQOS_Pos		(0U)
#define PA_QOS_URGENT_CTL_AWQOS_Msk		(0xfUL << PA_QOS_URGENT_CTL_AWQOS_Pos)
#define PA_QOS_URGENT_CTL_AWQOS    		PA_QOS_URGENT_CTL_AWQOS_Msk


/****************************** Bit definition for PHY_CTL_IO_REG0 register ********************************/

#define PHY_CTL_IO_REG0_CTRL_IO_CK_Pos		(31U)
#define PHY_CTL_IO_REG0_CTRL_IO_CK_Msk		(0x1UL << PHY_CTL_IO_REG0_CTRL_IO_CK_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_CK    		PHY_CTL_IO_REG0_CTRL_IO_CK_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_CK_EN_Pos		(30U)
#define PHY_CTL_IO_REG0_CTRL_IO_CK_EN_Msk		(0x1UL << PHY_CTL_IO_REG0_CTRL_IO_CK_EN_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_CK_EN    		PHY_CTL_IO_REG0_CTRL_IO_CK_EN_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE_Pos		(27U)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE_Msk		(0x1UL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE    		PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE_Pos		(26U)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE_Msk		(0x1UL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE    		PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_CS_EN_Pos		(24U)
#define PHY_CTL_IO_REG0_CTRL_IO_CS_EN_Msk		(0x3UL << PHY_CTL_IO_REG0_CTRL_IO_CS_EN_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_CS_EN    		PHY_CTL_IO_REG0_CTRL_IO_CS_EN_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_CS_Pos		(22U)
#define PHY_CTL_IO_REG0_CTRL_IO_CS_Msk		(0x3UL << PHY_CTL_IO_REG0_CTRL_IO_CS_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_CS    		PHY_CTL_IO_REG0_CTRL_IO_CS_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_ODT_EN_Pos		(20U)
#define PHY_CTL_IO_REG0_CTRL_IO_ODT_EN_Msk		(0x3UL << PHY_CTL_IO_REG0_CTRL_IO_ODT_EN_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_ODT_EN    		PHY_CTL_IO_REG0_CTRL_IO_ODT_EN_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_ODT_Pos		(18U)
#define PHY_CTL_IO_REG0_CTRL_IO_ODT_Msk		(0x3UL << PHY_CTL_IO_REG0_CTRL_IO_ODT_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_ODT    		PHY_CTL_IO_REG0_CTRL_IO_ODT_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_RESET_EN_Pos		(17U)
#define PHY_CTL_IO_REG0_CTRL_IO_RESET_EN_Msk		(0x1UL << PHY_CTL_IO_REG0_CTRL_IO_RESET_EN_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_RESET_EN    		PHY_CTL_IO_REG0_CTRL_IO_RESET_EN_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_RESET_Pos		(16U)
#define PHY_CTL_IO_REG0_CTRL_IO_RESET_Msk		(0x1UL << PHY_CTL_IO_REG0_CTRL_IO_RESET_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_RESET    		PHY_CTL_IO_REG0_CTRL_IO_RESET_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_Pos		(8U)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_Msk		(0x7fUL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN    		PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_Msk


#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_Pos		(0U)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT_Msk		(0x7fUL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_Pos)
#define PHY_CTL_IO_REG0_CTRL_IO_ADCT    		PHY_CTL_IO_REG0_CTRL_IO_ADCT_Msk


/****************************** Bit definition for PHY_CTL_IO_SLICE0 register ********************************/

#define PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN_Pos		(26U)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN_Msk		(0x1UL << PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN_Pos)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN    		PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN_Msk


#define PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN_Pos		(25U)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN_Msk		(0x1UL << PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN_Pos)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN    		PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN_Msk


#define PHY_CTL_IO_SLICE0_CTRL_IO_DW_Pos		(24U)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DW_Msk		(0x1UL << PHY_CTL_IO_SLICE0_CTRL_IO_DW_Pos)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DW    		PHY_CTL_IO_SLICE0_CTRL_IO_DW_Msk


#define PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN_Pos		(16U)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN_Msk		(0xffUL << PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN_Pos)
#define PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN    		PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN_Msk


#define PHY_CTL_IO_SLICE0_CTRL_IO_WDQS_Pos		(8U)
#define PHY_CTL_IO_SLICE0_CTRL_IO_WDQS_Msk		(0x1UL << PHY_CTL_IO_SLICE0_CTRL_IO_WDQS_Pos)
#define PHY_CTL_IO_SLICE0_CTRL_IO_WDQS    		PHY_CTL_IO_SLICE0_CTRL_IO_WDQS_Msk


#define PHY_CTL_IO_SLICE0_CTRL_IO_WDATA_Pos		(0U)
#define PHY_CTL_IO_SLICE0_CTRL_IO_WDATA_Msk		(0xffUL << PHY_CTL_IO_SLICE0_CTRL_IO_WDATA_Pos)
#define PHY_CTL_IO_SLICE0_CTRL_IO_WDATA    		PHY_CTL_IO_SLICE0_CTRL_IO_WDATA_Msk


/****************************** Bit definition for PHY_CTL_IO_SLICE1 register ********************************/

#define PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN_Pos		(26U)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN_Msk		(0x1UL << PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN_Pos)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN    		PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN_Msk


#define PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN_Pos		(25U)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN_Msk		(0x1UL << PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN_Pos)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN    		PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN_Msk


#define PHY_CTL_IO_SLICE1_CTRL_IO_DW_Pos		(24U)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DW_Msk		(0x1UL << PHY_CTL_IO_SLICE1_CTRL_IO_DW_Pos)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DW    		PHY_CTL_IO_SLICE1_CTRL_IO_DW_Msk


#define PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN_Pos		(16U)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN_Msk		(0xffUL << PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN_Pos)
#define PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN    		PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN_Msk


#define PHY_CTL_IO_SLICE1_CTRL_IO_WDQS_Pos		(8U)
#define PHY_CTL_IO_SLICE1_CTRL_IO_WDQS_Msk		(0x1UL << PHY_CTL_IO_SLICE1_CTRL_IO_WDQS_Pos)
#define PHY_CTL_IO_SLICE1_CTRL_IO_WDQS    		PHY_CTL_IO_SLICE1_CTRL_IO_WDQS_Msk


#define PHY_CTL_IO_SLICE1_CTRL_IO_WDATA_Pos		(0U)
#define PHY_CTL_IO_SLICE1_CTRL_IO_WDATA_Msk		(0xffUL << PHY_CTL_IO_SLICE1_CTRL_IO_WDATA_Pos)
#define PHY_CTL_IO_SLICE1_CTRL_IO_WDATA    		PHY_CTL_IO_SLICE1_CTRL_IO_WDATA_Msk


/****************************** Bit definition for PHY_CTL_IO_STATUS0 register ********************************/

#define PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN_Pos		(31U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN_Msk		(0x1UL << PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN    		PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN_Msk


#define PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN_Pos		(29U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN_Msk		(0x3UL << PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN    		PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN_Msk


#define PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN_Pos		(22U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN_Msk		(0x7fUL << PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN    		PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN_Msk


#define PHY_CTL_IO_STATUS0_CTRL_IO_RDM_Pos		(20U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RDM_Msk		(0x3UL << PHY_CTL_IO_STATUS0_CTRL_IO_RDM_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RDM    		PHY_CTL_IO_STATUS0_CTRL_IO_RDM_Msk


#define PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS_Pos		(18U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS_Msk		(0x3UL << PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS    		PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS_Msk


#define PHY_CTL_IO_STATUS0_CTRL_IO_RDQS_Pos		(16U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RDQS_Msk		(0x3UL << PHY_CTL_IO_STATUS0_CTRL_IO_RDQS_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RDQS    		PHY_CTL_IO_STATUS0_CTRL_IO_RDQS_Msk


#define PHY_CTL_IO_STATUS0_CTRL_IO_RDATA_Pos		(0U)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RDATA_Msk		(0xffffUL << PHY_CTL_IO_STATUS0_CTRL_IO_RDATA_Pos)
#define PHY_CTL_IO_STATUS0_CTRL_IO_RDATA    		PHY_CTL_IO_STATUS0_CTRL_IO_RDATA_Msk


/****************************** Bit definition for PHY_CTL_IO_STATUS1 register ********************************/

#define PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN_Pos		(1U)
#define PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN_Msk		(0x1UL << PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN_Pos)
#define PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN    		PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN_Msk


#define PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE_Pos		(0U)
#define PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE_Msk		(0x1UL << PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE_Pos)
#define PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE    		PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE_Msk


/****************************** Bit definition for PARMASK register ********************************/

#define PARMASK_PAR_MASK_RED_Pos		(1U)
#define PARMASK_PAR_MASK_RED_Msk		(0x1UL << PARMASK_PAR_MASK_RED_Pos)
#define PARMASK_PAR_MASK_RED    		PARMASK_PAR_MASK_RED_Msk


#define PARMASK_PAR_MASK_BLUE_Pos		(0U)
#define PARMASK_PAR_MASK_BLUE_Msk		(0x1UL << PARMASK_PAR_MASK_BLUE_Pos)
#define PARMASK_PAR_MASK_BLUE    		PARMASK_PAR_MASK_BLUE_Msk


/****************************** Bit definition for PAWMASK register ********************************/

/****************************** Bit definition for RST_CTL register ********************************/

#define RST_CTL_PLL_RESETB_Pos		(7U)
#define RST_CTL_PLL_RESETB_Msk		(0x1UL << RST_CTL_PLL_RESETB_Pos)
#define RST_CTL_PLL_RESETB    		RST_CTL_PLL_RESETB_Msk


#define RST_CTL_PHY2X_CLKGATE_ENABLE_Pos		(6U)
#define RST_CTL_PHY2X_CLKGATE_ENABLE_Msk		(0x1UL << RST_CTL_PHY2X_CLKGATE_ENABLE_Pos)
#define RST_CTL_PHY2X_CLKGATE_ENABLE    		RST_CTL_PHY2X_CLKGATE_ENABLE_Msk


#define RST_CTL_RESETN_DDRPHY_Pos		(5U)
#define RST_CTL_RESETN_DDRPHY_Msk		(0x1UL << RST_CTL_RESETN_DDRPHY_Pos)
#define RST_CTL_RESETN_DDRPHY    		RST_CTL_RESETN_DDRPHY_Msk


#define RST_CTL_DIV_RSTN_DDRPHY_Pos		(4U)
#define RST_CTL_DIV_RSTN_DDRPHY_Msk		(0x1UL << RST_CTL_DIV_RSTN_DDRPHY_Pos)
#define RST_CTL_DIV_RSTN_DDRPHY    		RST_CTL_DIV_RSTN_DDRPHY_Msk


#define RST_CTL_PRESETN_DDRPHY_Pos		(3U)
#define RST_CTL_PRESETN_DDRPHY_Msk		(0x1UL << RST_CTL_PRESETN_DDRPHY_Pos)
#define RST_CTL_PRESETN_DDRPHY    		RST_CTL_PRESETN_DDRPHY_Msk


#define RST_CTL_RSTN_DDRPHY_Pos		(2U)
#define RST_CTL_RSTN_DDRPHY_Msk		(0x1UL << RST_CTL_RSTN_DDRPHY_Pos)
#define RST_CTL_RSTN_DDRPHY    		RST_CTL_RSTN_DDRPHY_Msk


#define RST_CTL_PRESETN_DDRCTL_Pos		(1U)
#define RST_CTL_PRESETN_DDRCTL_Msk		(0x1UL << RST_CTL_PRESETN_DDRCTL_Pos)
#define RST_CTL_PRESETN_DDRCTL    		RST_CTL_PRESETN_DDRCTL_Msk


#define RST_CTL_CORE_DDRC_RSTN_Pos		(0U)
#define RST_CTL_CORE_DDRC_RSTN_Msk		(0x1UL << RST_CTL_CORE_DDRC_RSTN_Pos)
#define RST_CTL_CORE_DDRC_RSTN    		RST_CTL_CORE_DDRC_RSTN_Msk


/****************************** Bit definition for DDRCTL_STATUS register ********************************/

#define DDRCTL_STATUS_DDRCTL_SELFREF_TYPE_Pos		(24U)
#define DDRCTL_STATUS_DDRCTL_SELFREF_TYPE_Msk		(0xffUL << DDRCTL_STATUS_DDRCTL_SELFREF_TYPE_Pos)
#define DDRCTL_STATUS_DDRCTL_SELFREF_TYPE    		DDRCTL_STATUS_DDRCTL_SELFREF_TYPE_Msk


#define DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE_Pos		(16U)
#define DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE_Msk		(0x7UL << DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE_Pos)
#define DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE    		DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE_Msk


#define DDRCTL_STATUS_DFI_ERROR_Pos		(13U)
#define DDRCTL_STATUS_DFI_ERROR_Msk		(0x1UL << DDRCTL_STATUS_DFI_ERROR_Pos)
#define DDRCTL_STATUS_DFI_ERROR    		DDRCTL_STATUS_DFI_ERROR_Msk


#define DDRCTL_STATUS_DDRCTL_INTR_Pos		(0U)
#define DDRCTL_STATUS_DDRCTL_INTR_Msk		(0x1fffUL << DDRCTL_STATUS_DDRCTL_INTR_Pos)
#define DDRCTL_STATUS_DDRCTL_INTR    		DDRCTL_STATUS_DDRCTL_INTR_Msk


/****************************** Bit definition for DDRPHY_STATUS0 register ********************************/

#define DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE_Pos		(31U)
#define DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE_Msk		(0x1UL << DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE_Pos)
#define DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE    		DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE_Msk


#define DDRPHY_STATUS0_TEST_EXT_LB_MON_Pos		(21U)
#define DDRPHY_STATUS0_TEST_EXT_LB_MON_Msk		(0x3ffUL << DDRPHY_STATUS0_TEST_EXT_LB_MON_Pos)
#define DDRPHY_STATUS0_TEST_EXT_LB_MON    		DDRPHY_STATUS0_TEST_EXT_LB_MON_Msk


#define DDRPHY_STATUS0_TEST_OKY_Pos		(12U)
#define DDRPHY_STATUS0_TEST_OKY_Msk		(0x1ffUL << DDRPHY_STATUS0_TEST_OKY_Pos)
#define DDRPHY_STATUS0_TEST_OKY    		DDRPHY_STATUS0_TEST_OKY_Msk


#define DDRPHY_STATUS0_ND_DDR_END_Pos		(11U)
#define DDRPHY_STATUS0_ND_DDR_END_Msk		(0x1UL << DDRPHY_STATUS0_ND_DDR_END_Pos)
#define DDRPHY_STATUS0_ND_DDR_END    		DDRPHY_STATUS0_ND_DDR_END_Msk


#define DDRPHY_STATUS0_TEST_ERR_Pos		(0U)
#define DDRPHY_STATUS0_TEST_ERR_Msk		(0x1ffUL << DDRPHY_STATUS0_TEST_ERR_Pos)
#define DDRPHY_STATUS0_TEST_ERR    		DDRPHY_STATUS0_TEST_ERR_Msk


/****************************** Bit definition for DDRPHY_STATUS1 register ********************************/

#define DDRPHY_STATUS1_TEST_EXT_ZQ_END_Pos		(6U)
#define DDRPHY_STATUS1_TEST_EXT_ZQ_END_Msk		(0x1UL << DDRPHY_STATUS1_TEST_EXT_ZQ_END_Pos)
#define DDRPHY_STATUS1_TEST_EXT_ZQ_END    		DDRPHY_STATUS1_TEST_EXT_ZQ_END_Msk


#define DDRPHY_STATUS1_TEST_EXT_ZQ_NMON_Pos		(3U)
#define DDRPHY_STATUS1_TEST_EXT_ZQ_NMON_Msk		(0x7UL << DDRPHY_STATUS1_TEST_EXT_ZQ_NMON_Pos)
#define DDRPHY_STATUS1_TEST_EXT_ZQ_NMON    		DDRPHY_STATUS1_TEST_EXT_ZQ_NMON_Msk


#define DDRPHY_STATUS1_TEST_EXT_ZQ_PMON_Pos		(0U)
#define DDRPHY_STATUS1_TEST_EXT_ZQ_PMON_Msk		(0x7UL << DDRPHY_STATUS1_TEST_EXT_ZQ_PMON_Pos)
#define DDRPHY_STATUS1_TEST_EXT_ZQ_PMON    		DDRPHY_STATUS1_TEST_EXT_ZQ_PMON_Msk


/****************************** Bit definition for DDRPHY_PINS_CTL register ********************************/

#define DDRPHY_PINS_CTL_RST_IOV_LPDDR4_Pos		(19U)
#define DDRPHY_PINS_CTL_RST_IOV_LPDDR4_Msk		(0x1UL << DDRPHY_PINS_CTL_RST_IOV_LPDDR4_Pos)
#define DDRPHY_PINS_CTL_RST_IOV_LPDDR4    		DDRPHY_PINS_CTL_RST_IOV_LPDDR4_Msk


#define DDRPHY_PINS_CTL_RETON_LPDDR4_Pos		(18U)
#define DDRPHY_PINS_CTL_RETON_LPDDR4_Msk		(0x1UL << DDRPHY_PINS_CTL_RETON_LPDDR4_Pos)
#define DDRPHY_PINS_CTL_RETON_LPDDR4    		DDRPHY_PINS_CTL_RETON_LPDDR4_Msk


#define DDRPHY_PINS_CTL_RETOFF_LPDDR4_Pos		(17U)
#define DDRPHY_PINS_CTL_RETOFF_LPDDR4_Msk		(0x1UL << DDRPHY_PINS_CTL_RETOFF_LPDDR4_Pos)
#define DDRPHY_PINS_CTL_RETOFF_LPDDR4    		DDRPHY_PINS_CTL_RETOFF_LPDDR4_Msk


#define DDRPHY_PINS_CTL_ND_DDR_START_Pos		(16U)
#define DDRPHY_PINS_CTL_ND_DDR_START_Msk		(0x1UL << DDRPHY_PINS_CTL_ND_DDR_START_Pos)
#define DDRPHY_PINS_CTL_ND_DDR_START    		DDRPHY_PINS_CTL_ND_DDR_START_Msk


#define DDRPHY_PINS_CTL_MODE_RUN_Pos		(13U)
#define DDRPHY_PINS_CTL_MODE_RUN_Msk		(0x7UL << DDRPHY_PINS_CTL_MODE_RUN_Pos)
#define DDRPHY_PINS_CTL_MODE_RUN    		DDRPHY_PINS_CTL_MODE_RUN_Msk


#define DDRPHY_PINS_CTL_MODE_HIGHZ_Pos		(12U)
#define DDRPHY_PINS_CTL_MODE_HIGHZ_Msk		(0x1UL << DDRPHY_PINS_CTL_MODE_HIGHZ_Pos)
#define DDRPHY_PINS_CTL_MODE_HIGHZ    		DDRPHY_PINS_CTL_MODE_HIGHZ_Msk


#define DDRPHY_PINS_CTL_MODE_MUX_Pos		(11U)
#define DDRPHY_PINS_CTL_MODE_MUX_Msk		(0x1UL << DDRPHY_PINS_CTL_MODE_MUX_Pos)
#define DDRPHY_PINS_CTL_MODE_MUX    		DDRPHY_PINS_CTL_MODE_MUX_Msk


#define DDRPHY_PINS_CTL_MODE_SCAN_Pos		(10U)
#define DDRPHY_PINS_CTL_MODE_SCAN_Msk		(0x1UL << DDRPHY_PINS_CTL_MODE_SCAN_Pos)
#define DDRPHY_PINS_CTL_MODE_SCAN    		DDRPHY_PINS_CTL_MODE_SCAN_Msk


#define DDRPHY_PINS_CTL_MODE_NAND_Pos		(9U)
#define DDRPHY_PINS_CTL_MODE_NAND_Msk		(0x1UL << DDRPHY_PINS_CTL_MODE_NAND_Pos)
#define DDRPHY_PINS_CTL_MODE_NAND    		DDRPHY_PINS_CTL_MODE_NAND_Msk


#define DDRPHY_PINS_CTL_MODE_PHY_Pos		(8U)
#define DDRPHY_PINS_CTL_MODE_PHY_Msk		(0x1UL << DDRPHY_PINS_CTL_MODE_PHY_Pos)
#define DDRPHY_PINS_CTL_MODE_PHY    		DDRPHY_PINS_CTL_MODE_PHY_Msk


#define DDRPHY_PINS_CTL_DVFS_CLK_MODE_Pos		(5U)
#define DDRPHY_PINS_CTL_DVFS_CLK_MODE_Msk		(0x3UL << DDRPHY_PINS_CTL_DVFS_CLK_MODE_Pos)
#define DDRPHY_PINS_CTL_DVFS_CLK_MODE    		DDRPHY_PINS_CTL_DVFS_CLK_MODE_Msk


#define DDRPHY_PINS_CTL_I_G_DRCG_EN_Pos		(4U)
#define DDRPHY_PINS_CTL_I_G_DRCG_EN_Msk		(0x1UL << DDRPHY_PINS_CTL_I_G_DRCG_EN_Pos)
#define DDRPHY_PINS_CTL_I_G_DRCG_EN    		DDRPHY_PINS_CTL_I_G_DRCG_EN_Msk


#define DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_Pos		(1U)
#define DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_Msk		(0x7UL << DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_Pos)
#define DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN    		DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_Msk


#define DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER_Pos		(0U)
#define DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER_Msk		(0x1UL << DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER_Pos)
#define DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER    		DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER_Msk


/****************************** Bit definition for DDRPHY_PINS_TEST_CTL register ********************************/

#define DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN_Pos		(31U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN    		DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN_Pos		(30U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN    		DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_READ_Pos		(29U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_READ_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_READ_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_READ    		DDRPHY_PINS_TEST_CTL_TEST_EXT_READ_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT_Pos		(28U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT    		DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_EN_Pos		(27U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_EN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_EN_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_EN    		DDRPHY_PINS_TEST_CTL_TEST_EXT_EN_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC_Pos		(24U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC_Msk		(0x7UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC    		DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD_Pos		(14U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD_Msk		(0x3ffUL << DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD    		DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF_Pos		(13U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF    		DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT_Pos		(5U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT_Msk		(0xffUL << DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT    		DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV_Pos		(4U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV    		DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE_Pos		(1U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE_Msk		(0x7UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE    		DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE_Msk


#define DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS_Pos		(0U)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS_Pos)
#define DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS    		DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS_Msk


/****************************** Bit definition for DDRPHY_PINS_TEST_CTL2 register ********************************/

#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW_Pos		(20U)
#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW_Msk		(0x3ffUL << DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW_Pos)
#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW    		DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW_Msk


#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR_Pos		(10U)
#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR_Msk		(0x3ffUL << DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR_Pos)
#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR    		DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR_Msk


#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC_Pos		(0U)
#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC_Msk		(0x3ffUL << DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC_Pos)
#define DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC    		DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC_Msk


/****************************** Bit definition for DDRPHY_PINS_TEST_CTL3 register ********************************/

#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN_Pos		(31U)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN_Pos)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN    		DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN_Msk


#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN_Pos		(30U)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN_Pos)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN    		DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN_Msk


#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN_Pos		(29U)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN_Pos)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN    		DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN_Msk


#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN_Pos		(28U)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN_Pos)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN    		DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN_Msk


#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE_Pos		(24U)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE_Msk		(0xfUL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE_Pos)
#define DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE    		DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE_Msk


#define DDRPHY_PINS_TEST_CTL3_TEST_START_Pos		(0U)
#define DDRPHY_PINS_TEST_CTL3_TEST_START_Msk		(0xffUL << DDRPHY_PINS_TEST_CTL3_TEST_START_Pos)
#define DDRPHY_PINS_TEST_CTL3_TEST_START    		DDRPHY_PINS_TEST_CTL3_TEST_START_Msk


/****************************** Bit definition for DDRPHY_PINS_TEST_CTL4 register ********************************/

#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE_Pos		(8U)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE_Msk		(0xffffffUL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE_Pos)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE    		DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE_Msk


#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL_Pos		(6U)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL_Msk		(0x3UL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL_Pos)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL    		DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL_Msk


#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN_Pos		(4U)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN_Msk		(0x3UL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN_Pos)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN    		DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN_Msk


#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG_Pos		(0U)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG_Msk		(0xfUL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG_Pos)
#define DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG    		DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG_Msk


/****************************** Bit definition for DDRPHY_PINS_TEST_CTL5 register ********************************/

#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF_Pos		(26U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF_Msk		(0x3fUL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS_Pos		(23U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS_Msk		(0x7UL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS_Pos		(20U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS_Msk		(0x7UL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN_Pos		(17U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN_Msk		(0x7UL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP_Pos		(14U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP_Msk		(0x7UL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_Pos		(13U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX_Pos		(7U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX_Msk		(0x3fUL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN_Pos		(1U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN_Msk		(0x3fUL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN_Msk


#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST_Pos		(0U)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST_Msk		(0x1UL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST_Pos)
#define DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST    		DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST_Msk


/****************************** Bit definition for DDRPHY_PLL_CTL register ********************************/

#define DDRPHY_PLL_CTL_LOCK_EN_Pos		(31U)
#define DDRPHY_PLL_CTL_LOCK_EN_Msk		(0x1UL << DDRPHY_PLL_CTL_LOCK_EN_Pos)
#define DDRPHY_PLL_CTL_LOCK_EN    		DDRPHY_PLL_CTL_LOCK_EN_Msk


#define DDRPHY_PLL_CTL_LOCK_CON_DLY_Pos		(29U)
#define DDRPHY_PLL_CTL_LOCK_CON_DLY_Msk		(0x3UL << DDRPHY_PLL_CTL_LOCK_CON_DLY_Pos)
#define DDRPHY_PLL_CTL_LOCK_CON_DLY    		DDRPHY_PLL_CTL_LOCK_CON_DLY_Msk


#define DDRPHY_PLL_CTL_LOCK_CON_OUT_Pos		(27U)
#define DDRPHY_PLL_CTL_LOCK_CON_OUT_Msk		(0x3UL << DDRPHY_PLL_CTL_LOCK_CON_OUT_Pos)
#define DDRPHY_PLL_CTL_LOCK_CON_OUT    		DDRPHY_PLL_CTL_LOCK_CON_OUT_Msk


#define DDRPHY_PLL_CTL_LOCK_CON_IN_Pos		(25U)
#define DDRPHY_PLL_CTL_LOCK_CON_IN_Msk		(0x3UL << DDRPHY_PLL_CTL_LOCK_CON_IN_Pos)
#define DDRPHY_PLL_CTL_LOCK_CON_IN    		DDRPHY_PLL_CTL_LOCK_CON_IN_Msk


#define DDRPHY_PLL_CTL_FOUT_MASK_Pos		(24U)
#define DDRPHY_PLL_CTL_FOUT_MASK_Msk		(0x1UL << DDRPHY_PLL_CTL_FOUT_MASK_Pos)
#define DDRPHY_PLL_CTL_FOUT_MASK    		DDRPHY_PLL_CTL_FOUT_MASK_Msk


#define DDRPHY_PLL_CTL_PSEL_Pos		(23U)
#define DDRPHY_PLL_CTL_PSEL_Msk		(0x1UL << DDRPHY_PLL_CTL_PSEL_Pos)
#define DDRPHY_PLL_CTL_PSEL    		DDRPHY_PLL_CTL_PSEL_Msk


#define DDRPHY_PLL_CTL_FEED_EN_Pos		(22U)
#define DDRPHY_PLL_CTL_FEED_EN_Msk		(0x1UL << DDRPHY_PLL_CTL_FEED_EN_Pos)
#define DDRPHY_PLL_CTL_FEED_EN    		DDRPHY_PLL_CTL_FEED_EN_Msk


#define DDRPHY_PLL_CTL_AFC_ENB_Pos		(21U)
#define DDRPHY_PLL_CTL_AFC_ENB_Msk		(0x1UL << DDRPHY_PLL_CTL_AFC_ENB_Pos)
#define DDRPHY_PLL_CTL_AFC_ENB    		DDRPHY_PLL_CTL_AFC_ENB_Msk


#define DDRPHY_PLL_CTL_BYPASS_Pos		(20U)
#define DDRPHY_PLL_CTL_BYPASS_Msk		(0x1UL << DDRPHY_PLL_CTL_BYPASS_Pos)
#define DDRPHY_PLL_CTL_BYPASS    		DDRPHY_PLL_CTL_BYPASS_Msk


#define DDRPHY_PLL_CTL_SSCG_EN_Pos		(19U)
#define DDRPHY_PLL_CTL_SSCG_EN_Msk		(0x1UL << DDRPHY_PLL_CTL_SSCG_EN_Pos)
#define DDRPHY_PLL_CTL_SSCG_EN    		DDRPHY_PLL_CTL_SSCG_EN_Msk


#define DDRPHY_PLL_CTL_S_Pos		(16U)
#define DDRPHY_PLL_CTL_S_Msk		(0x7UL << DDRPHY_PLL_CTL_S_Pos)
#define DDRPHY_PLL_CTL_S    		DDRPHY_PLL_CTL_S_Msk


#define DDRPHY_PLL_CTL_M_Pos		(6U)
#define DDRPHY_PLL_CTL_M_Msk		(0x3ffUL << DDRPHY_PLL_CTL_M_Pos)
#define DDRPHY_PLL_CTL_M    		DDRPHY_PLL_CTL_M_Msk


#define DDRPHY_PLL_CTL_P_Pos		(0U)
#define DDRPHY_PLL_CTL_P_Msk		(0x3fUL << DDRPHY_PLL_CTL_P_Pos)
#define DDRPHY_PLL_CTL_P    		DDRPHY_PLL_CTL_P_Msk


/****************************** Bit definition for DDRPHY_PLL_CTL2 register ********************************/

#define DDRPHY_PLL_CTL2_K_Pos		(0U)
#define DDRPHY_PLL_CTL2_K_Msk		(0xffffUL << DDRPHY_PLL_CTL2_K_Pos)
#define DDRPHY_PLL_CTL2_K    		DDRPHY_PLL_CTL2_K_Msk


/****************************** Bit definition for DDRPHY_PLL_CTL3 register ********************************/

#define DDRPHY_PLL_CTL3_ICP_Pos		(21U)
#define DDRPHY_PLL_CTL3_ICP_Msk		(0x3UL << DDRPHY_PLL_CTL3_ICP_Pos)
#define DDRPHY_PLL_CTL3_ICP    		DDRPHY_PLL_CTL3_ICP_Msk


#define DDRPHY_PLL_CTL3_EXTAFC_Pos		(16U)
#define DDRPHY_PLL_CTL3_EXTAFC_Msk		(0x1fUL << DDRPHY_PLL_CTL3_EXTAFC_Pos)
#define DDRPHY_PLL_CTL3_EXTAFC    		DDRPHY_PLL_CTL3_EXTAFC_Msk


#define DDRPHY_PLL_CTL3_SEL_PF_Pos		(14U)
#define DDRPHY_PLL_CTL3_SEL_PF_Msk		(0x3UL << DDRPHY_PLL_CTL3_SEL_PF_Pos)
#define DDRPHY_PLL_CTL3_SEL_PF    		DDRPHY_PLL_CTL3_SEL_PF_Msk


#define DDRPHY_PLL_CTL3_MRR_Pos		(8U)
#define DDRPHY_PLL_CTL3_MRR_Msk		(0x3fUL << DDRPHY_PLL_CTL3_MRR_Pos)
#define DDRPHY_PLL_CTL3_MRR    		DDRPHY_PLL_CTL3_MRR_Msk


#define DDRPHY_PLL_CTL3_MFR_Pos		(0U)
#define DDRPHY_PLL_CTL3_MFR_Msk		(0xffUL << DDRPHY_PLL_CTL3_MFR_Pos)
#define DDRPHY_PLL_CTL3_MFR    		DDRPHY_PLL_CTL3_MFR_Msk


/****************************** Bit definition for DDRPHY_PLL_CTL4 register ********************************/

#define DDRPHY_PLL_CTL4_CTR_Pos		(16U)
#define DDRPHY_PLL_CTL4_CTR_Msk		(0xffffUL << DDRPHY_PLL_CTL4_CTR_Pos)
#define DDRPHY_PLL_CTL4_CTR    		DDRPHY_PLL_CTL4_CTR_Msk


#define DDRPHY_PLL_CTL4_RSEL_Pos		(0U)
#define DDRPHY_PLL_CTL4_RSEL_Msk		(0xffffUL << DDRPHY_PLL_CTL4_RSEL_Pos)
#define DDRPHY_PLL_CTL4_RSEL    		DDRPHY_PLL_CTL4_RSEL_Msk


/****************************** Bit definition for DDRPHY_PLL_STATUS register ********************************/

#define DDRPHY_PLL_STATUS_AFC_CODE_Pos		(16U)
#define DDRPHY_PLL_STATUS_AFC_CODE_Msk		(0x1fUL << DDRPHY_PLL_STATUS_AFC_CODE_Pos)
#define DDRPHY_PLL_STATUS_AFC_CODE    		DDRPHY_PLL_STATUS_AFC_CODE_Msk


#define DDRPHY_PLL_STATUS_FEED_OUT_Pos		(8U)
#define DDRPHY_PLL_STATUS_FEED_OUT_Msk		(0x1UL << DDRPHY_PLL_STATUS_FEED_OUT_Pos)
#define DDRPHY_PLL_STATUS_FEED_OUT    		DDRPHY_PLL_STATUS_FEED_OUT_Msk


#define DDRPHY_PLL_STATUS_LOCKED_Pos		(0U)
#define DDRPHY_PLL_STATUS_LOCKED_Msk		(0x1UL << DDRPHY_PLL_STATUS_LOCKED_Pos)
#define DDRPHY_PLL_STATUS_LOCKED    		DDRPHY_PLL_STATUS_LOCKED_Msk


/****************************** Inline function for PA_QOS_URGENT_CTL register ********************************/

static inline void set_arpoison_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARPOISON_ENABLE, VAL << PA_QOS_URGENT_CTL_ARPOISON_ENABLE_Pos);
}

static inline uint32_t get_arpoison_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARPOISON_ENABLE) >> PA_QOS_URGENT_CTL_ARPOISON_ENABLE_Pos);
}

static inline void set_arpoison(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARPOISON, VAL << PA_QOS_URGENT_CTL_ARPOISON_Pos);
}

static inline uint32_t get_arpoison(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARPOISON) >> PA_QOS_URGENT_CTL_ARPOISON_Pos);
}

static inline void set_awpoison_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWPOISON_ENABLE, VAL << PA_QOS_URGENT_CTL_AWPOISON_ENABLE_Pos);
}

static inline uint32_t get_awpoison_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWPOISON_ENABLE) >> PA_QOS_URGENT_CTL_AWPOISON_ENABLE_Pos);
}

static inline void set_awpoison(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWPOISON, VAL << PA_QOS_URGENT_CTL_AWPOISON_Pos);
}

static inline uint32_t get_awpoison(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWPOISON) >> PA_QOS_URGENT_CTL_AWPOISON_Pos);
}

static inline void set_arrugentr_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE, VAL << PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE_Pos);
}

static inline uint32_t get_arrugentr_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE) >> PA_QOS_URGENT_CTL_ARRUGENTR_ENABLE_Pos);
}

static inline void set_arrugentr(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTR, VAL << PA_QOS_URGENT_CTL_ARRUGENTR_Pos);
}

static inline uint32_t get_arrugentr(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTR) >> PA_QOS_URGENT_CTL_ARRUGENTR_Pos);
}

static inline void set_arrugentb_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE, VAL << PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE_Pos);
}

static inline uint32_t get_arrugentb_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE) >> PA_QOS_URGENT_CTL_ARRUGENTB_ENABLE_Pos);
}

static inline void set_arrugentb(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTB, VAL << PA_QOS_URGENT_CTL_ARRUGENTB_Pos);
}

static inline uint32_t get_arrugentb(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARRUGENTB) >> PA_QOS_URGENT_CTL_ARRUGENTB_Pos);
}

static inline void set_awrugent_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWRUGENT_ENABLE, VAL << PA_QOS_URGENT_CTL_AWRUGENT_ENABLE_Pos);
}

static inline uint32_t get_awrugent_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWRUGENT_ENABLE) >> PA_QOS_URGENT_CTL_AWRUGENT_ENABLE_Pos);
}

static inline void set_awurgent(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWURGENT, VAL << PA_QOS_URGENT_CTL_AWURGENT_Pos);
}

static inline uint32_t get_awurgent(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWURGENT) >> PA_QOS_URGENT_CTL_AWURGENT_Pos);
}

static inline void set_arqos_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARQOS_ENABLE, VAL << PA_QOS_URGENT_CTL_ARQOS_ENABLE_Pos);
}

static inline uint32_t get_arqos_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARQOS_ENABLE) >> PA_QOS_URGENT_CTL_ARQOS_ENABLE_Pos);
}

static inline void set_arqos(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARQOS, VAL << PA_QOS_URGENT_CTL_ARQOS_Pos);
}

static inline uint32_t get_arqos(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_ARQOS) >> PA_QOS_URGENT_CTL_ARQOS_Pos);
}

static inline void set_awqos_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWQOS_ENABLE, VAL << PA_QOS_URGENT_CTL_AWQOS_ENABLE_Pos);
}

static inline uint32_t get_awqos_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWQOS_ENABLE) >> PA_QOS_URGENT_CTL_AWQOS_ENABLE_Pos);
}

static inline void set_awqos(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWQOS, VAL << PA_QOS_URGENT_CTL_AWQOS_Pos);
}

static inline uint32_t get_awqos(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PA_QOS_URGENT_CTL, PA_QOS_URGENT_CTL_AWQOS) >> PA_QOS_URGENT_CTL_AWQOS_Pos);
}

/****************************** Inline function for PHY_CTL_IO_REG0 register ********************************/

static inline void set_ctrl_io_ck(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CK, VAL << PHY_CTL_IO_REG0_CTRL_IO_CK_Pos);
}

static inline uint32_t get_ctrl_io_ck(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CK) >> PHY_CTL_IO_REG0_CTRL_IO_CK_Pos);
}

static inline void set_ctrl_io_ck_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CK_EN, VAL << PHY_CTL_IO_REG0_CTRL_IO_CK_EN_Pos);
}

static inline uint32_t get_ctrl_io_ck_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CK_EN) >> PHY_CTL_IO_REG0_CTRL_IO_CK_EN_Pos);
}

static inline void set_ctrl_io_adct_en_swizzle(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE, VAL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE_Pos);
}

static inline uint32_t get_ctrl_io_adct_en_swizzle(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE) >> PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_SWIZZLE_Pos);
}

static inline void set_ctrl_io_adct_swizzle(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE, VAL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE_Pos);
}

static inline uint32_t get_ctrl_io_adct_swizzle(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE) >> PHY_CTL_IO_REG0_CTRL_IO_ADCT_SWIZZLE_Pos);
}

static inline void set_ctrl_io_cs_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CS_EN, VAL << PHY_CTL_IO_REG0_CTRL_IO_CS_EN_Pos);
}

static inline uint32_t get_ctrl_io_cs_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CS_EN) >> PHY_CTL_IO_REG0_CTRL_IO_CS_EN_Pos);
}

static inline void set_ctrl_io_cs(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CS, VAL << PHY_CTL_IO_REG0_CTRL_IO_CS_Pos);
}

static inline uint32_t get_ctrl_io_cs(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_CS) >> PHY_CTL_IO_REG0_CTRL_IO_CS_Pos);
}

static inline void set_ctrl_io_odt_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ODT_EN, VAL << PHY_CTL_IO_REG0_CTRL_IO_ODT_EN_Pos);
}

static inline uint32_t get_ctrl_io_odt_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ODT_EN) >> PHY_CTL_IO_REG0_CTRL_IO_ODT_EN_Pos);
}

static inline void set_ctrl_io_odt(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ODT, VAL << PHY_CTL_IO_REG0_CTRL_IO_ODT_Pos);
}

static inline uint32_t get_ctrl_io_odt(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ODT) >> PHY_CTL_IO_REG0_CTRL_IO_ODT_Pos);
}

static inline void set_ctrl_io_reset_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_RESET_EN, VAL << PHY_CTL_IO_REG0_CTRL_IO_RESET_EN_Pos);
}

static inline uint32_t get_ctrl_io_reset_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_RESET_EN) >> PHY_CTL_IO_REG0_CTRL_IO_RESET_EN_Pos);
}

static inline void set_ctrl_io_reset(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_RESET, VAL << PHY_CTL_IO_REG0_CTRL_IO_RESET_Pos);
}

static inline uint32_t get_ctrl_io_reset(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_RESET) >> PHY_CTL_IO_REG0_CTRL_IO_RESET_Pos);
}

static inline void set_ctrl_io_adct_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN, VAL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_Pos);
}

static inline uint32_t get_ctrl_io_adct_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN) >> PHY_CTL_IO_REG0_CTRL_IO_ADCT_EN_Pos);
}

static inline void set_ctrl_io_adct(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT, VAL << PHY_CTL_IO_REG0_CTRL_IO_ADCT_Pos);
}

static inline uint32_t get_ctrl_io_adct(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_REG0, PHY_CTL_IO_REG0_CTRL_IO_ADCT) >> PHY_CTL_IO_REG0_CTRL_IO_ADCT_Pos);
}

/****************************** Inline function for PHY_CTL_IO_SLICE0 register ********************************/

static inline void set_ctrl_io_dqs_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN, VAL << PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN_Pos);
}

static inline uint32_t get_ctrl_io_dqs_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN) >> PHY_CTL_IO_SLICE0_CTRL_IO_DQS_EN_Pos);
}

static inline void set_ctrl_io_dw_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN, VAL << PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN_Pos);
}

static inline uint32_t get_ctrl_io_dw_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN) >> PHY_CTL_IO_SLICE0_CTRL_IO_DW_EN_Pos);
}

static inline void set_ctrl_io_dw(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DW, VAL << PHY_CTL_IO_SLICE0_CTRL_IO_DW_Pos);
}

static inline uint32_t get_ctrl_io_dw(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DW) >> PHY_CTL_IO_SLICE0_CTRL_IO_DW_Pos);
}

static inline void set_ctrl_io_data_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN, VAL << PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN_Pos);
}

static inline uint32_t get_ctrl_io_data_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN) >> PHY_CTL_IO_SLICE0_CTRL_IO_DATA_EN_Pos);
}

static inline void set_ctrl_io_wdqs(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_WDQS, VAL << PHY_CTL_IO_SLICE0_CTRL_IO_WDQS_Pos);
}

static inline uint32_t get_ctrl_io_wdqs(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_WDQS) >> PHY_CTL_IO_SLICE0_CTRL_IO_WDQS_Pos);
}

static inline void set_ctrl_io_wdata(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_WDATA, VAL << PHY_CTL_IO_SLICE0_CTRL_IO_WDATA_Pos);
}

static inline uint32_t get_ctrl_io_wdata(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE0, PHY_CTL_IO_SLICE0_CTRL_IO_WDATA) >> PHY_CTL_IO_SLICE0_CTRL_IO_WDATA_Pos);
}

/****************************** Inline function for PHY_CTL_IO_SLICE1 register ********************************/

static inline void set_ctrl_io_dqs_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN, VAL << PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN_Pos);
}

static inline uint32_t get_ctrl_io_dqs_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN) >> PHY_CTL_IO_SLICE1_CTRL_IO_DQS_EN_Pos);
}

static inline void set_ctrl_io_dw_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN, VAL << PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN_Pos);
}

static inline uint32_t get_ctrl_io_dw_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN) >> PHY_CTL_IO_SLICE1_CTRL_IO_DW_EN_Pos);
}

static inline void set_ctrl_io_dw(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DW, VAL << PHY_CTL_IO_SLICE1_CTRL_IO_DW_Pos);
}

static inline uint32_t get_ctrl_io_dw(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DW) >> PHY_CTL_IO_SLICE1_CTRL_IO_DW_Pos);
}

static inline void set_ctrl_io_data_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN, VAL << PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN_Pos);
}

static inline uint32_t get_ctrl_io_data_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN) >> PHY_CTL_IO_SLICE1_CTRL_IO_DATA_EN_Pos);
}

static inline void set_ctrl_io_wdqs(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_WDQS, VAL << PHY_CTL_IO_SLICE1_CTRL_IO_WDQS_Pos);
}

static inline uint32_t get_ctrl_io_wdqs(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_WDQS) >> PHY_CTL_IO_SLICE1_CTRL_IO_WDQS_Pos);
}

static inline void set_ctrl_io_wdata(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_WDATA, VAL << PHY_CTL_IO_SLICE1_CTRL_IO_WDATA_Pos);
}

static inline uint32_t get_ctrl_io_wdata(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_SLICE1, PHY_CTL_IO_SLICE1_CTRL_IO_WDATA) >> PHY_CTL_IO_SLICE1_CTRL_IO_WDATA_Pos);
}

/****************************** Inline function for PHY_CTL_IO_STATUS0 register ********************************/

static inline void set_ctrl_io_reset_in(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN_Pos);
}

static inline uint32_t get_ctrl_io_reset_in(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN) >> PHY_CTL_IO_STATUS0_CTRL_IO_RESET_IN_Pos);
}

static inline void set_ctrl_io_cs_in(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN_Pos);
}

static inline uint32_t get_ctrl_io_cs_in(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN) >> PHY_CTL_IO_STATUS0_CTRL_IO_CS_IN_Pos);
}

static inline void set_ctrl_io_adct_in(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN_Pos);
}

static inline uint32_t get_ctrl_io_adct_in(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN) >> PHY_CTL_IO_STATUS0_CTRL_IO_ADCT_IN_Pos);
}

static inline void set_ctrl_io_rdm(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RDM, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_RDM_Pos);
}

static inline uint32_t get_ctrl_io_rdm(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RDM) >> PHY_CTL_IO_STATUS0_CTRL_IO_RDM_Pos);
}

static inline void set_ctrl_io_rndqs(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS_Pos);
}

static inline uint32_t get_ctrl_io_rndqs(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS) >> PHY_CTL_IO_STATUS0_CTRL_IO_RNDQS_Pos);
}

static inline void set_ctrl_io_rdqs(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RDQS, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_RDQS_Pos);
}

static inline uint32_t get_ctrl_io_rdqs(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RDQS) >> PHY_CTL_IO_STATUS0_CTRL_IO_RDQS_Pos);
}

static inline void set_ctrl_io_rdata(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RDATA, VAL << PHY_CTL_IO_STATUS0_CTRL_IO_RDATA_Pos);
}

static inline uint32_t get_ctrl_io_rdata(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS0, PHY_CTL_IO_STATUS0_CTRL_IO_RDATA) >> PHY_CTL_IO_STATUS0_CTRL_IO_RDATA_Pos);
}

/****************************** Inline function for PHY_CTL_IO_STATUS1 register ********************************/

static inline void set_ctrl_io_ck_in(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS1, PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN, VAL << PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN_Pos);
}

static inline uint32_t get_ctrl_io_ck_in(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS1, PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN) >> PHY_CTL_IO_STATUS1_CTRL_IO_CK_IN_Pos);
}

static inline void set_ctrl_io_adct_in_swzzle(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PHY_CTL_IO_STATUS1, PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE, VAL << PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE_Pos);
}

static inline uint32_t get_ctrl_io_adct_in_swzzle(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PHY_CTL_IO_STATUS1, PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE) >> PHY_CTL_IO_STATUS1_CTRL_IO_ADCT_IN_SWZZLE_Pos);
}

/****************************** Inline function for PARMASK register ********************************/

static inline void set_par_mask_red(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PARMASK, PARMASK_PAR_MASK_RED, VAL << PARMASK_PAR_MASK_RED_Pos);
}

static inline uint32_t get_par_mask_red(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PARMASK, PARMASK_PAR_MASK_RED) >> PARMASK_PAR_MASK_RED_Pos);
}

static inline void set_par_mask_blue(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PARMASK, PARMASK_PAR_MASK_BLUE, VAL << PARMASK_PAR_MASK_BLUE_Pos);
}

static inline uint32_t get_par_mask_blue(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PARMASK, PARMASK_PAR_MASK_BLUE) >> PARMASK_PAR_MASK_BLUE_Pos);
}

/****************************** Inline function for PAWMASK register ********************************/

/****************************** Inline function for RST_CTL register ********************************/

static inline void set_pll_resetb(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_PLL_RESETB, VAL << RST_CTL_PLL_RESETB_Pos);
}

static inline uint32_t get_pll_resetb(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_PLL_RESETB) >> RST_CTL_PLL_RESETB_Pos);
}

static inline void set_phy2x_clkgate_enable(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_PHY2X_CLKGATE_ENABLE, VAL << RST_CTL_PHY2X_CLKGATE_ENABLE_Pos);
}

static inline uint32_t get_phy2x_clkgate_enable(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_PHY2X_CLKGATE_ENABLE) >> RST_CTL_PHY2X_CLKGATE_ENABLE_Pos);
}

static inline void set_resetn_ddrphy(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_RESETN_DDRPHY, VAL << RST_CTL_RESETN_DDRPHY_Pos);
}

static inline uint32_t get_resetn_ddrphy(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_RESETN_DDRPHY) >> RST_CTL_RESETN_DDRPHY_Pos);
}

static inline void set_div_rstn_ddrphy(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_DIV_RSTN_DDRPHY, VAL << RST_CTL_DIV_RSTN_DDRPHY_Pos);
}

static inline uint32_t get_div_rstn_ddrphy(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_DIV_RSTN_DDRPHY) >> RST_CTL_DIV_RSTN_DDRPHY_Pos);
}

static inline void set_presetn_ddrphy(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_PRESETN_DDRPHY, VAL << RST_CTL_PRESETN_DDRPHY_Pos);
}

static inline uint32_t get_presetn_ddrphy(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_PRESETN_DDRPHY) >> RST_CTL_PRESETN_DDRPHY_Pos);
}

static inline void set_rstn_ddrphy(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_RSTN_DDRPHY, VAL << RST_CTL_RSTN_DDRPHY_Pos);
}

static inline uint32_t get_rstn_ddrphy(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_RSTN_DDRPHY) >> RST_CTL_RSTN_DDRPHY_Pos);
}

static inline void set_presetn_ddrctl(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_PRESETN_DDRCTL, VAL << RST_CTL_PRESETN_DDRCTL_Pos);
}

static inline uint32_t get_presetn_ddrctl(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_PRESETN_DDRCTL) >> RST_CTL_PRESETN_DDRCTL_Pos);
}

static inline void set_core_ddrc_rstn(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RST_CTL, RST_CTL_CORE_DDRC_RSTN, VAL << RST_CTL_CORE_DDRC_RSTN_Pos);
}

static inline uint32_t get_core_ddrc_rstn(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RST_CTL, RST_CTL_CORE_DDRC_RSTN) >> RST_CTL_CORE_DDRC_RSTN_Pos);
}

/****************************** Inline function for DDRCTL_STATUS register ********************************/

static inline void set_ddrctl_selfref_type(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRCTL_STATUS, DDRCTL_STATUS_DDRCTL_SELFREF_TYPE, VAL << DDRCTL_STATUS_DDRCTL_SELFREF_TYPE_Pos);
}

static inline uint32_t get_ddrctl_selfref_type(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRCTL_STATUS, DDRCTL_STATUS_DDRCTL_SELFREF_TYPE) >> DDRCTL_STATUS_DDRCTL_SELFREF_TYPE_Pos);
}

static inline void set_dbg_dfi_ie_cmd_type(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRCTL_STATUS, DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE, VAL << DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE_Pos);
}

static inline uint32_t get_dbg_dfi_ie_cmd_type(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRCTL_STATUS, DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE) >> DDRCTL_STATUS_DBG_DFI_IE_CMD_TYPE_Pos);
}

static inline void set_dfi_error(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRCTL_STATUS, DDRCTL_STATUS_DFI_ERROR, VAL << DDRCTL_STATUS_DFI_ERROR_Pos);
}

static inline uint32_t get_dfi_error(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRCTL_STATUS, DDRCTL_STATUS_DFI_ERROR) >> DDRCTL_STATUS_DFI_ERROR_Pos);
}

static inline void set_ddrctl_intr(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRCTL_STATUS, DDRCTL_STATUS_DDRCTL_INTR, VAL << DDRCTL_STATUS_DDRCTL_INTR_Pos);
}

static inline uint32_t get_ddrctl_intr(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRCTL_STATUS, DDRCTL_STATUS_DDRCTL_INTR) >> DDRCTL_STATUS_DDRCTL_INTR_Pos);
}

/****************************** Inline function for DDRPHY_STATUS0 register ********************************/

static inline void set_test_ext_init_complete(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE, VAL << DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE_Pos);
}

static inline uint32_t get_test_ext_init_complete(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE) >> DDRPHY_STATUS0_TEST_EXT_INIT_COMPLETE_Pos);
}

static inline void set_test_ext_lb_mon(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_EXT_LB_MON, VAL << DDRPHY_STATUS0_TEST_EXT_LB_MON_Pos);
}

static inline uint32_t get_test_ext_lb_mon(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_EXT_LB_MON) >> DDRPHY_STATUS0_TEST_EXT_LB_MON_Pos);
}

static inline void set_test_oky(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_OKY, VAL << DDRPHY_STATUS0_TEST_OKY_Pos);
}

static inline uint32_t get_test_oky(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_OKY) >> DDRPHY_STATUS0_TEST_OKY_Pos);
}

static inline void set_nd_ddr_end(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_ND_DDR_END, VAL << DDRPHY_STATUS0_ND_DDR_END_Pos);
}

static inline uint32_t get_nd_ddr_end(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_ND_DDR_END) >> DDRPHY_STATUS0_ND_DDR_END_Pos);
}

static inline void set_test_err(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_ERR, VAL << DDRPHY_STATUS0_TEST_ERR_Pos);
}

static inline uint32_t get_test_err(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS0, DDRPHY_STATUS0_TEST_ERR) >> DDRPHY_STATUS0_TEST_ERR_Pos);
}

/****************************** Inline function for DDRPHY_STATUS1 register ********************************/

static inline void set_test_ext_zq_end(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS1, DDRPHY_STATUS1_TEST_EXT_ZQ_END, VAL << DDRPHY_STATUS1_TEST_EXT_ZQ_END_Pos);
}

static inline uint32_t get_test_ext_zq_end(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS1, DDRPHY_STATUS1_TEST_EXT_ZQ_END) >> DDRPHY_STATUS1_TEST_EXT_ZQ_END_Pos);
}

static inline void set_test_ext_zq_nmon(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS1, DDRPHY_STATUS1_TEST_EXT_ZQ_NMON, VAL << DDRPHY_STATUS1_TEST_EXT_ZQ_NMON_Pos);
}

static inline uint32_t get_test_ext_zq_nmon(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS1, DDRPHY_STATUS1_TEST_EXT_ZQ_NMON) >> DDRPHY_STATUS1_TEST_EXT_ZQ_NMON_Pos);
}

static inline void set_test_ext_zq_pmon(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_STATUS1, DDRPHY_STATUS1_TEST_EXT_ZQ_PMON, VAL << DDRPHY_STATUS1_TEST_EXT_ZQ_PMON_Pos);
}

static inline uint32_t get_test_ext_zq_pmon(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_STATUS1, DDRPHY_STATUS1_TEST_EXT_ZQ_PMON) >> DDRPHY_STATUS1_TEST_EXT_ZQ_PMON_Pos);
}

/****************************** Inline function for DDRPHY_PINS_CTL register ********************************/

static inline void set_rst_iov_lpddr4(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_RST_IOV_LPDDR4, VAL << DDRPHY_PINS_CTL_RST_IOV_LPDDR4_Pos);
}

static inline uint32_t get_rst_iov_lpddr4(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_RST_IOV_LPDDR4) >> DDRPHY_PINS_CTL_RST_IOV_LPDDR4_Pos);
}

static inline void set_reton_lpddr4(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_RETON_LPDDR4, VAL << DDRPHY_PINS_CTL_RETON_LPDDR4_Pos);
}

static inline uint32_t get_reton_lpddr4(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_RETON_LPDDR4) >> DDRPHY_PINS_CTL_RETON_LPDDR4_Pos);
}

static inline void set_retoff_lpddr4(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_RETOFF_LPDDR4, VAL << DDRPHY_PINS_CTL_RETOFF_LPDDR4_Pos);
}

static inline uint32_t get_retoff_lpddr4(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_RETOFF_LPDDR4) >> DDRPHY_PINS_CTL_RETOFF_LPDDR4_Pos);
}

static inline void set_nd_ddr_start(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_ND_DDR_START, VAL << DDRPHY_PINS_CTL_ND_DDR_START_Pos);
}

static inline uint32_t get_nd_ddr_start(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_ND_DDR_START) >> DDRPHY_PINS_CTL_ND_DDR_START_Pos);
}

static inline void set_mode_run(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_RUN, VAL << DDRPHY_PINS_CTL_MODE_RUN_Pos);
}

static inline uint32_t get_mode_run(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_RUN) >> DDRPHY_PINS_CTL_MODE_RUN_Pos);
}

static inline void set_mode_highz(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_HIGHZ, VAL << DDRPHY_PINS_CTL_MODE_HIGHZ_Pos);
}

static inline uint32_t get_mode_highz(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_HIGHZ) >> DDRPHY_PINS_CTL_MODE_HIGHZ_Pos);
}

static inline void set_mode_mux(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_MUX, VAL << DDRPHY_PINS_CTL_MODE_MUX_Pos);
}

static inline uint32_t get_mode_mux(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_MUX) >> DDRPHY_PINS_CTL_MODE_MUX_Pos);
}

static inline void set_mode_scan(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_SCAN, VAL << DDRPHY_PINS_CTL_MODE_SCAN_Pos);
}

static inline uint32_t get_mode_scan(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_SCAN) >> DDRPHY_PINS_CTL_MODE_SCAN_Pos);
}

static inline void set_mode_nand(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_NAND, VAL << DDRPHY_PINS_CTL_MODE_NAND_Pos);
}

static inline uint32_t get_mode_nand(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_NAND) >> DDRPHY_PINS_CTL_MODE_NAND_Pos);
}

static inline void set_mode_phy(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_PHY, VAL << DDRPHY_PINS_CTL_MODE_PHY_Pos);
}

static inline uint32_t get_mode_phy(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_MODE_PHY) >> DDRPHY_PINS_CTL_MODE_PHY_Pos);
}

static inline void set_dvfs_clk_mode(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_DVFS_CLK_MODE, VAL << DDRPHY_PINS_CTL_DVFS_CLK_MODE_Pos);
}

static inline uint32_t get_dvfs_clk_mode(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_DVFS_CLK_MODE) >> DDRPHY_PINS_CTL_DVFS_CLK_MODE_Pos);
}

static inline void set_i_g_drcg_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_I_G_DRCG_EN, VAL << DDRPHY_PINS_CTL_I_G_DRCG_EN_Pos);
}

static inline uint32_t get_i_g_drcg_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_I_G_DRCG_EN) >> DDRPHY_PINS_CTL_I_G_DRCG_EN_Pos);
}

static inline void set_ctrl_clkm_cg_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN, VAL << DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_Pos);
}

static inline uint32_t get_ctrl_clkm_cg_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN) >> DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_Pos);
}

static inline void set_ctrl_clkm_cg_en_inter(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER, VAL << DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER_Pos);
}

static inline uint32_t get_ctrl_clkm_cg_en_inter(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_CTL, DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER) >> DDRPHY_PINS_CTL_CTRL_CLKM_CG_EN_INTER_Pos);
}

/****************************** Inline function for DDRPHY_PINS_TEST_CTL register ********************************/

static inline void set_test_ext_auto_dqs_clean(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN_Pos);
}

static inline uint32_t get_test_ext_auto_dqs_clean(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_AUTO_DQS_CLEAN_Pos);
}

static inline void set_test_ext_dfe_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN_Pos);
}

static inline uint32_t get_test_ext_dfe_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_DFE_EN_Pos);
}

static inline void set_test_ext_read(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_READ, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_READ_Pos);
}

static inline uint32_t get_test_ext_read(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_READ) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_READ_Pos);
}

static inline void set_test_ext_out(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT_Pos);
}

static inline uint32_t get_test_ext_out(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_OUT_Pos);
}

static inline void set_test_ext_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_EN, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_EN_Pos);
}

static inline uint32_t get_test_ext_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_EN) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_EN_Pos);
}

static inline void set_test_ext_shiftc(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC_Pos);
}

static inline uint32_t get_test_ext_shiftc(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_SHIFTC_Pos);
}

static inline void set_test_ext_offsetd(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD_Pos);
}

static inline uint32_t get_test_ext_offsetd(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_OFFSETD_Pos);
}

static inline void set_test_ext_half(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF_Pos);
}

static inline uint32_t get_test_ext_half(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_HALF_Pos);
}

static inline void set_test_ext_start_point(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT_Pos);
}

static inline uint32_t get_test_ext_start_point(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_START_POINT_Pos);
}

static inline void set_test_ext_cmosrcv(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV_Pos);
}

static inline uint32_t get_test_ext_cmosrcv(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_CMOSRCV_Pos);
}

static inline void set_test_ext_phy_mode(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE_Pos);
}

static inline uint32_t get_test_ext_phy_mode(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_PHY_MODE_Pos);
}

static inline void set_test_ext_dfdqs(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS, VAL << DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS_Pos);
}

static inline uint32_t get_test_ext_dfdqs(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL, DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS) >> DDRPHY_PINS_TEST_CTL_TEST_EXT_DFDQS_Pos);
}

/****************************** Inline function for DDRPHY_PINS_TEST_CTL2 register ********************************/

static inline void set_test_ext_offsetw(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL2, DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW, VAL << DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW_Pos);
}

static inline uint32_t get_test_ext_offsetw(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL2, DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW) >> DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETW_Pos);
}

static inline void set_test_ext_offsetr(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL2, DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR, VAL << DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR_Pos);
}

static inline uint32_t get_test_ext_offsetr(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL2, DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR) >> DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETR_Pos);
}

static inline void set_test_ext_offsetc(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL2, DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC, VAL << DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC_Pos);
}

static inline uint32_t get_test_ext_offsetc(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL2, DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC) >> DDRPHY_PINS_TEST_CTL2_TEST_EXT_OFFSETC_Pos);
}

/****************************** Inline function for DDRPHY_PINS_TEST_CTL3 register ********************************/

static inline void set_test_ext_gatelvl_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN, VAL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN_Pos);
}

static inline uint32_t get_test_ext_gatelvl_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN) >> DDRPHY_PINS_TEST_CTL3_TEST_EXT_GATELVL_EN_Pos);
}

static inline void set_test_ext_rdlvl_wr_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN, VAL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN_Pos);
}

static inline uint32_t get_test_ext_rdlvl_wr_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN) >> DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_WR_EN_Pos);
}

static inline void set_test_ext_rdlvl_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN, VAL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN_Pos);
}

static inline uint32_t get_test_ext_rdlvl_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN) >> DDRPHY_PINS_TEST_CTL3_TEST_EXT_RDLVL_EN_Pos);
}

static inline void set_test_ext_write_lvl_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN, VAL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN_Pos);
}

static inline uint32_t get_test_ext_write_lvl_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN) >> DDRPHY_PINS_TEST_CTL3_TEST_EXT_WRITE_LVL_EN_Pos);
}

static inline void set_test_ext_mode(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE, VAL << DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE_Pos);
}

static inline uint32_t get_test_ext_mode(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE) >> DDRPHY_PINS_TEST_CTL3_TEST_EXT_MODE_Pos);
}

static inline void set_test_start(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_START, VAL << DDRPHY_PINS_TEST_CTL3_TEST_START_Pos);
}

static inline uint32_t get_test_start(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL3, DDRPHY_PINS_TEST_CTL3_TEST_START) >> DDRPHY_PINS_TEST_CTL3_TEST_START_Pos);
}

/****************************** Inline function for DDRPHY_PINS_TEST_CTL4 register ********************************/

static inline void set_test_ext_ds_rcv_mode(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE, VAL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE_Pos);
}

static inline uint32_t get_test_ext_ds_rcv_mode(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE) >> DDRPHY_PINS_TEST_CTL4_TEST_EXT_DS_RCV_MODE_Pos);
}

static inline void set_test_ext_lb_mon_sel(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL, VAL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL_Pos);
}

static inline uint32_t get_test_ext_lb_mon_sel(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL) >> DDRPHY_PINS_TEST_CTL4_TEST_EXT_LB_MON_SEL_Pos);
}

static inline void set_test_ext_margin(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN, VAL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN_Pos);
}

static inline uint32_t get_test_ext_margin(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN) >> DDRPHY_PINS_TEST_CTL4_TEST_EXT_MARGIN_Pos);
}

static inline void set_test_ext_debug(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG, VAL << DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG_Pos);
}

static inline uint32_t get_test_ext_debug(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL4, DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG) >> DDRPHY_PINS_TEST_CTL4_TEST_EXT_DEBUG_Pos);
}

/****************************** Inline function for DDRPHY_PINS_TEST_CTL5 register ********************************/

static inline void set_test_ext_zq_mode_vref(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF_Pos);
}

static inline uint32_t get_test_ext_zq_mode_vref(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_VREF_Pos);
}

static inline void set_test_ext_zq_mode_pdds(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS_Pos);
}

static inline uint32_t get_test_ext_zq_mode_pdds(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_PDDS_Pos);
}

static inline void set_test_ext_zq_mode_dds(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS_Pos);
}

static inline uint32_t get_test_ext_zq_mode_dds(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_MODE_DDS_Pos);
}

static inline void set_test_ext_zq_force_impn(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN_Pos);
}

static inline uint32_t get_test_ext_zq_force_impn(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPN_Pos);
}

static inline void set_test_ext_zq_force_impp(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP_Pos);
}

static inline uint32_t get_test_ext_zq_force_impp(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_IMPP_Pos);
}

static inline void set_test_ext_zq_force(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_Pos);
}

static inline uint32_t get_test_ext_zq_force(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_ZQ_FORCE_Pos);
}

static inline void set_test_ext_vref_max(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX_Pos);
}

static inline uint32_t get_test_ext_vref_max(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MAX_Pos);
}

static inline void set_test_ext_vref_min(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN_Pos);
}

static inline uint32_t get_test_ext_vref_min(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_MIN_Pos);
}

static inline void set_test_ext_vref_test(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST, VAL << DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST_Pos);
}

static inline uint32_t get_test_ext_vref_test(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PINS_TEST_CTL5, DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST) >> DDRPHY_PINS_TEST_CTL5_TEST_EXT_VREF_TEST_Pos);
}

/****************************** Inline function for DDRPHY_PLL_CTL register ********************************/

static inline void set_lock_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_EN, VAL << DDRPHY_PLL_CTL_LOCK_EN_Pos);
}

static inline uint32_t get_lock_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_EN) >> DDRPHY_PLL_CTL_LOCK_EN_Pos);
}

static inline void set_lock_con_dly(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_CON_DLY, VAL << DDRPHY_PLL_CTL_LOCK_CON_DLY_Pos);
}

static inline uint32_t get_lock_con_dly(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_CON_DLY) >> DDRPHY_PLL_CTL_LOCK_CON_DLY_Pos);
}

static inline void set_lock_con_out(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_CON_OUT, VAL << DDRPHY_PLL_CTL_LOCK_CON_OUT_Pos);
}

static inline uint32_t get_lock_con_out(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_CON_OUT) >> DDRPHY_PLL_CTL_LOCK_CON_OUT_Pos);
}

static inline void set_lock_con_in(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_CON_IN, VAL << DDRPHY_PLL_CTL_LOCK_CON_IN_Pos);
}

static inline uint32_t get_lock_con_in(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_LOCK_CON_IN) >> DDRPHY_PLL_CTL_LOCK_CON_IN_Pos);
}

static inline void set_fout_mask(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_FOUT_MASK, VAL << DDRPHY_PLL_CTL_FOUT_MASK_Pos);
}

static inline uint32_t get_fout_mask(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_FOUT_MASK) >> DDRPHY_PLL_CTL_FOUT_MASK_Pos);
}

static inline void set_psel(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_PSEL, VAL << DDRPHY_PLL_CTL_PSEL_Pos);
}

static inline uint32_t get_psel(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_PSEL) >> DDRPHY_PLL_CTL_PSEL_Pos);
}

static inline void set_feed_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_FEED_EN, VAL << DDRPHY_PLL_CTL_FEED_EN_Pos);
}

static inline uint32_t get_feed_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_FEED_EN) >> DDRPHY_PLL_CTL_FEED_EN_Pos);
}

static inline void set_afc_enb(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_AFC_ENB, VAL << DDRPHY_PLL_CTL_AFC_ENB_Pos);
}

static inline uint32_t get_afc_enb(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_AFC_ENB) >> DDRPHY_PLL_CTL_AFC_ENB_Pos);
}

static inline void set_bypass(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_BYPASS, VAL << DDRPHY_PLL_CTL_BYPASS_Pos);
}

static inline uint32_t get_bypass(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_BYPASS) >> DDRPHY_PLL_CTL_BYPASS_Pos);
}

static inline void set_sscg_en(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_SSCG_EN, VAL << DDRPHY_PLL_CTL_SSCG_EN_Pos);
}

static inline uint32_t get_sscg_en(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_SSCG_EN) >> DDRPHY_PLL_CTL_SSCG_EN_Pos);
}

static inline void set_s(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_S, VAL << DDRPHY_PLL_CTL_S_Pos);
}

static inline uint32_t get_s(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_S) >> DDRPHY_PLL_CTL_S_Pos);
}

static inline void set_m(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_M, VAL << DDRPHY_PLL_CTL_M_Pos);
}

static inline uint32_t get_m(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_M) >> DDRPHY_PLL_CTL_M_Pos);
}

static inline void set_p(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_P, VAL << DDRPHY_PLL_CTL_P_Pos);
}

static inline uint32_t get_p(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL, DDRPHY_PLL_CTL_P) >> DDRPHY_PLL_CTL_P_Pos);
}

/****************************** Inline function for DDRPHY_PLL_CTL2 register ********************************/

static inline void set_k(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL2, DDRPHY_PLL_CTL2_K, VAL << DDRPHY_PLL_CTL2_K_Pos);
}

static inline uint32_t get_k(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL2, DDRPHY_PLL_CTL2_K) >> DDRPHY_PLL_CTL2_K_Pos);
}

/****************************** Inline function for DDRPHY_PLL_CTL3 register ********************************/

static inline void set_icp(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_ICP, VAL << DDRPHY_PLL_CTL3_ICP_Pos);
}

static inline uint32_t get_icp(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_ICP) >> DDRPHY_PLL_CTL3_ICP_Pos);
}

static inline void set_extafc(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_EXTAFC, VAL << DDRPHY_PLL_CTL3_EXTAFC_Pos);
}

static inline uint32_t get_extafc(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_EXTAFC) >> DDRPHY_PLL_CTL3_EXTAFC_Pos);
}

static inline void set_sel_pf(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_SEL_PF, VAL << DDRPHY_PLL_CTL3_SEL_PF_Pos);
}

static inline uint32_t get_sel_pf(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_SEL_PF) >> DDRPHY_PLL_CTL3_SEL_PF_Pos);
}

static inline void set_mrr(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_MRR, VAL << DDRPHY_PLL_CTL3_MRR_Pos);
}

static inline uint32_t get_mrr(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_MRR) >> DDRPHY_PLL_CTL3_MRR_Pos);
}

static inline void set_mfr(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_MFR, VAL << DDRPHY_PLL_CTL3_MFR_Pos);
}

static inline uint32_t get_mfr(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL3, DDRPHY_PLL_CTL3_MFR) >> DDRPHY_PLL_CTL3_MFR_Pos);
}

/****************************** Inline function for DDRPHY_PLL_CTL4 register ********************************/

static inline void set_ctr(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL4, DDRPHY_PLL_CTL4_CTR, VAL << DDRPHY_PLL_CTL4_CTR_Pos);
}

static inline uint32_t get_ctr(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL4, DDRPHY_PLL_CTL4_CTR) >> DDRPHY_PLL_CTL4_CTR_Pos);
}

static inline void set_rsel(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_CTL4, DDRPHY_PLL_CTL4_RSEL, VAL << DDRPHY_PLL_CTL4_RSEL_Pos);
}

static inline uint32_t get_rsel(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_CTL4, DDRPHY_PLL_CTL4_RSEL) >> DDRPHY_PLL_CTL4_RSEL_Pos);
}

/****************************** Inline function for DDRPHY_PLL_STATUS register ********************************/

static inline void set_afc_code(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_STATUS, DDRPHY_PLL_STATUS_AFC_CODE, VAL << DDRPHY_PLL_STATUS_AFC_CODE_Pos);
}

static inline uint32_t get_afc_code(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_STATUS, DDRPHY_PLL_STATUS_AFC_CODE) >> DDRPHY_PLL_STATUS_AFC_CODE_Pos);
}

static inline void set_feed_out(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_STATUS, DDRPHY_PLL_STATUS_FEED_OUT, VAL << DDRPHY_PLL_STATUS_FEED_OUT_Pos);
}

static inline uint32_t get_feed_out(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_STATUS, DDRPHY_PLL_STATUS_FEED_OUT) >> DDRPHY_PLL_STATUS_FEED_OUT_Pos);
}

static inline void set_locked(LPDDR5_SGR_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRPHY_PLL_STATUS, DDRPHY_PLL_STATUS_LOCKED, VAL << DDRPHY_PLL_STATUS_LOCKED_Pos);
}

static inline uint32_t get_locked(LPDDR5_SGR_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRPHY_PLL_STATUS, DDRPHY_PLL_STATUS_LOCKED) >> DDRPHY_PLL_STATUS_LOCKED_Pos);
}

#endif // __LPDDR5_SGR_H__